xlli_mainstone_defs.inc
来自「该BSP是基于PXA270+WINCE的BSP」· INC 代码 · 共 484 行 · 第 1/2 页
INC
484 行
;*********************************************************************************
;
; COPYRIGHT (c) 2002 - 2004 Intel Corporation
;
; The information in this file is furnished for informational use only,
; is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
;
;*********************************************************************************
;
; FILENAME: xlli_Mainstone_defs.inc (Platform specific addresses and
; defalut values for Mainstone II platform bring up)
; NOTE: - This file has a def to configure xlli for MCP and non-MCP processors
;
; LAST MODIFIED: 13-Feb-2004
;
;******************************************************************************
;
;
; Include file for Mainstone II specific Cross Platform Low Level Initialization (XLLI)
;
;
; PLATFORM REGISTERS base address and register offsets from the base address
;
xlli_PLATFORM_REGISTERS EQU 0x08000000
xlli_PLATFORM_HEXLED_DATA_offset EQU (0x10) ; Hex LED Data Register
xlli_PLATFORM_LED_CONTROL_offset EQU (0x40) ; LED Control Register
xlli_PLATFORM_SWITCH_offset EQU (0x60) ; General Purpose Switch Register
xlli_PLATFORM_MISC_WRITE1_offset EQU (0x80) ; Misc Write Register 1
xlli_PLATFORM_MISC_WRITE2_offset EQU (0x84) ; Misc Write Register 2
xlli_PLATFORM_MISC_READ1_offset EQU (0x90) ; Misc Read Register 1
xlli_PLATFORM_INTERR_ME_offset EQU (0xC0) ; Platform Interrupt Mask/Enable Register 1
xlli_PLATFORM_INTERR_SC_offset EQU (0xD0) ; Platform Interrupt Set/Clear Register 1
xlli_PLATFORM_PCMCIA0_SC_offset EQU (0xE0) ; PCMCIA Socket 0 Status/Control Register
xlli_PLATFORM_PCMCIA1_SC_offset EQU (0xE4) ; PCMCIA Socket 1 Status/Control Register
;
; Platform specific bits
;
xlli_SYS_RESET EQU (0x01) ; System reset bit
;------------------------------------------------------------------------------------------------------
;
; platform GPIO pin settings (Bulverde/Mainstone)
;
;------------------------------
xlli_GPSR0_value EQU (0x00709C04) ;(0x00008004)
xlli_GPSR1_value EQU (0x00CF0002) ;(0x00000002) ; plus pcmcia
xlli_GPSR2_value EQU (0x0021C000) ;(0x0001FC00) ; plus pcmcia + mbgnt
xlli_GPSR3_value EQU (0x00020000) ;(0x00000000) ; Start with AC97 reset inactive (high)
;------------------------------
xlli_GPCR0_value EQU (0xC0040000) ;(0x0) ; AC sync and data out low
xlli_GPCR1_value EQU (0x00000380) ;(0x0) ; FFUART related
xlli_GPCR2_value EQU (0x00000000) ;(0x0)
xlli_GPCR3_value EQU (0x00000003) ;(0x0)
;------------------------------
xlli_GRER0_value EQU (0x0) ; Rising Edge Detect
xlli_GRER1_value EQU (0x0)
xlli_GRER2_value EQU (0x0)
xlli_GRER3_value EQU (0x0)
xlli_GFER0_value EQU (0x0) ; Falling Edge Detect
xlli_GFER1_value EQU (0x0)
xlli_GFER2_value EQU (0x0)
xlli_GFER3_value EQU (0x0)
;------------------------------
xlli_GPLR0_value EQU (0x0) ; Pin Level Registers
xlli_GPLR1_value EQU (0x0)
xlli_GPLR2_value EQU (0x0)
xlli_GPLR3_value EQU (0x0)
xlli_GEDR0_value EQU (0x0) ; Edge Detect Status
xlli_GEDR1_value EQU (0x0)
xlli_GEDR2_value EQU (0x0)
xlli_GEDR3_value EQU (0x0)
;------------------------------
xlli_GPDR0_value EQU (0x00709C04:OR:0xC0000000) ;(0x00088004) ; Direction Registers snake
xlli_GPDR1_value EQU (0x00CF0382) ;(0xFC000382) ; plus ffuart, PCMCIA and MBREQ/GNT
xlli_GPDR2_value EQU (0x0021C000) ;(0x00C1FFFF) ; plus pcmcia stuff
xlli_GPDR3_value EQU (0x00020002) ;(0x00000000) ; MBGNT (output) enabled + AC reset output
;------------------------------
;xlli_GAFR0_L_value EQU (0x90000000) ; Alternate function registers snake
;xlli_GAFR0_U_value EQU (0x00000010) ;00000000
;xlli_GAFR1_L_value EQU (0x000A9558) ;
;xlli_GAFR1_U_value EQU (0xAAA00000) ;
;xlli_GAFR2_L_value EQU (0x6AAAAAAA) ;0x2AAAAAAA
;xlli_GAFR2_U_value EQU (0x0000A002)
;xlli_GAFR3_L_value EQU (0x00000000)
;xlli_GAFR3_U_value EQU (0x00001400)
xlli_GAFR0_L_value EQU (0x84400000) ;(GPIO_11_AF1_EXTSYNC0_CHOUT0:OR:GPIO_13_AF1_CLKEXT:OR:GPIO_15_AF2_nCS1)
xlli_GAFR0_U_value EQU (0xA5000510) ;(GPIO_18_AF1_RDY:OR:GPIO_20_AF1_DREQ0_nSDCS2:OR:GPIO_21_AF1_nSDCS3:OR:GPIO_28_AF1_AC97_I2S_BITCLK:OR:GPIO_29_AF1_AC97SDATAIN0:OR:GPIO_30_AF2_AC97SDATAOUT:OR:GPIO_31_AF2_AC97SYNC)
xlli_GAFR1_L_value EQU (0x000A9558) ;(GPIO_33_AF2_nCS5:OR:GPIO_34_AF1_FFRXD:OR:GPIO_35_AF1_FFCTS:OR:GPIO_36_AF1_FFDCD:OR:GPIO_37_AF1_FFDSR:OR:GPIO_38_AF1_FFRI:OR:GPIO_39_AF2_FFTXD:OR:GPIO_40_AF2_FFDTR:OR:GPIO_41_AF2_FFRTS)
xlli_GAFR1_U_value EQU (0x0005A0AA) ;(GPIO_48_AF2_PCMCIAnPOE:OR:GPIO_49_AF2_nPWE:OR:GPIO_50_AF2_PCMCIAnPIOR:OR:GPIO_51_AF2_PCMCIAnPIOW:OR:GPIO_54_AF2_BBOBWAIT_PCMCIAnPCE2:OR:GPIO_55_AF2_BBIBDAT1_PCMCIAnPREG:OR:GPIO_56_AF1_PCMCIAnPWAIT:OR:GPIO_57_AF1_PCMCIAnIOIS16)
xlli_GAFR2_L_value EQU (0x20000000) ;;(GPIO_78_AF2_nCS2:OR:GPIO_79_AF1_PCMCIAPSKTSEL)
xlli_GAFR2_U_value EQU (0x00000402) ;(GPIO_80_AF2_MBREQ_nCS4:OR:GPIO_85_AF1_PCMCIAnPCE1)
xlli_GAFR3_L_value EQU (0x00000000)
xlli_GAFR3_U_value EQU (0x00000000)
;------------------------------------------------------------------------------------------------------
;
; MEMORY CONTROLLER SETTINGS FOR MAINSTONE
xlli_MDREFR_value EQU (0x2093A01E) ;(0x0000001E)
xlli_MSC0_DC_value EQU (0x39F2A7A2) ; Bulverde Card Flash value snake
xlli_MSC0_MS_value EQU (0x23F223F2) ; Mainstone Board Flash value
;---------------------------------------------
;xlli_MSC1_value EQU (0x0000A691)
xlli_MSC1_value EQU (0x0000FFF1)
;---------------------------------------------
;---------------------------------------------
;xlli_MSC2_value EQU (0xA691B884) ;//fixed, ok for lan91c111 B884
xlli_MSC2_value EQU (0xA6917FF9) ;//for dm9000
;---------------------------------------------
;----------------------------------
;xlli_MECR_value EQU (0x00000001)
xlli_MECR_value EQU (0x00000000) ;only one socket.pcmcia
;----------------------------------
xlli_MCMEM0_value EQU (0x0001C391)
xlli_MCMEM1_value EQU (0x0001C391)
xlli_MCATT0_value EQU (0x0001C391)
xlli_MCATT1_value EQU (0x0001C391)
xlli_MCIO0_value EQU (0x0001C391)
xlli_MCIO1_value EQU (0x0001C391)
xlli_FLYCNFG_value EQU (0x00010001)
xlli_MDMRSLP_value EQU (0x0000C008)
xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
;;xlli_MDREFR_value EQU (0x0000001E)
;; IF :DEF: xlli_FLASH_WIDTH_16_BIT
;;xlli_MSC0_DC_value EQU (0x7FF07FFA) ; Bulverde Card Flash value (MCP version)
;; ELSE
;;xlli_MSC0_DC_value EQU (0x7FF0B8F2) ; Bulverde Card Flash value (Non-MCP version)
;; ENDIF
;;xlli_MSC0_MS_value EQU (0x23F2B8F2) ; Mainstone Board Flash value
;;xlli_MSC1_value EQU (0x0000CCD1)
;;xlli_MSC2_value EQU (0x0000B884)
;;xlli_MECR_value EQU (0x00000001)
;;xlli_MCMEM0_value EQU (0x00014307)
;;xlli_MCMEM1_value EQU (0x00014307)
;;xlli_MCATT0_value EQU (0x0001C787)
;;xlli_MCATT1_value EQU (0x0001C787)
;;xlli_MCIO0_value EQU (0x0001430F)
;;xlli_MCIO1_value EQU (0x0001430F)
;;xlli_FLYCNFG_value EQU (0x00010001)
;;xlli_MDMRSLP_value EQU (0x0000C008)
;;xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
;
; Optimal values for MSCO for various MemClk frequencies are listed below
; These values are for L18 async flash
;
IF :DEF: xlli_C0_BULVERDE
xlli_MSC0_13 EQU (0x11101110)
xlli_MSC0_19 EQU (0x11101110)
xlli_MSC0_26 EQU (0x11201120) ; 26 MHz setting
xlli_MSC0_32 EQU (0x11201120)
xlli_MSC0_39 EQU (0x11301130) ; 39 MHz setting
xlli_MSC0_45 EQU (0x11301130)
xlli_MSC0_52 EQU (0x11401140) ; 52 MHz setting
xlli_MSC0_58 EQU (0x11401140)
xlli_MSC0_65 EQU (0x11501150) ; 65 MHz setting
xlli_MSC0_68 EQU (0x11501150)
xlli_MSC0_71 EQU (0x11501150) ; 71.5 MHz setting
xlli_MSC0_74 EQU (0x11601160)
xlli_MSC0_78 EQU (0x12601260) ; 78 MHz setting
xlli_MSC0_81 EQU (0x12601260)
xlli_MSC0_84 EQU (0x12601260) ; 84.5 MHz setting
xlli_MSC0_87 EQU (0x12701270)
xlli_MSC0_91 EQU (0x12701270) ; 91 MHz setting
xlli_MSC0_94 EQU (0x12701270) ; 94.2 MHz setting
xlli_MSC0_97 EQU (0x12701270) ; 97.5 MHz setting
xlli_MSC0_100 EQU (0x12801280) ; 100.7 MHz setting
xlli_MSC0_104 EQU (0x12801280) ; 104 MHz setting
xlli_MSC0_110 EQU (0x12901290)
xlli_MSC0_117 EQU (0x13901390) ; 117 MHz setting
xlli_MSC0_124 EQU (0x13A013A0)
xlli_MSC0_130 EQU (0x13A013A0) ; 130 MHz setting
xlli_MSC0_136 EQU (0x13B013B0)
xlli_MSC0_143 EQU (0x13B013B0)
xlli_MSC0_149 EQU (0x13C013C0)
xlli_MSC0_156 EQU (0x14C014C0)
xlli_MSC0_162 EQU (0x14C014C0)
xlli_MSC0_169 EQU (0x14C014C0)
xlli_MSC0_175 EQU (0x14C014C0)
xlli_MSC0_182 EQU (0x14C014C0)
xlli_MSC0_188 EQU (0x14C014C0)
xlli_MSC0_195 EQU (0x15C015C0)
xlli_MSC0_201 EQU (0x15D015D0)
xlli_MSC0_208 EQU (0x15D015D0)
ELSE
; This is a hack to get around some stupid B0 timing issue where it doesn't like the optimal
; values according to it's own SPEC!?! These timing values are relaxed from the above optimal
; but they work for B-step Bulverde... ugh....
xlli_MSC0_13 EQU (0x12101210)
xlli_MSC0_19 EQU (0x12101210)
xlli_MSC0_26 EQU (0x12201220) ; 26 MHz setting
xlli_MSC0_32 EQU (0x12201220)
xlli_MSC0_39 EQU (0x13301330) ; 39 MHz setting
xlli_MSC0_45 EQU (0x13301330)
xlli_MSC0_52 EQU (0x13401340) ; 52 MHz setting
xlli_MSC0_58 EQU (0x13601360)
xlli_MSC0_65 EQU (0x13501350) ; 65 MHz setting
xlli_MSC0_68 EQU (0x13501350)
xlli_MSC0_71 EQU (0x14601460) ; 71.5 MHz setting
xlli_MSC0_74 EQU (0x14601460)
xlli_MSC0_78 EQU (0x14601460) ; 78 MHz setting
xlli_MSC0_81 EQU (0x14701470)
xlli_MSC0_84 EQU (0x14701470) ; 84.5 MHz setting
xlli_MSC0_87 EQU (0x14701470)
xlli_MSC0_91 EQU (0x14701470) ; 91 MHz setting
xlli_MSC0_94 EQU (0x14801480) ; 94.2 MHz setting
xlli_MSC0_97 EQU (0x14801480) ; 97.5 MHz setting
xlli_MSC0_100 EQU (0x15801580) ; 100.7 MHz setting
xlli_MSC0_104 EQU (0x15801580) ; 104 MHz setting
xlli_MSC0_110 EQU (0x15901590)
xlli_MSC0_117 EQU (0x15A015A0) ; 117 MHz setting
xlli_MSC0_124 EQU (0x15A015A0)
xlli_MSC0_130 EQU (0x15B015B0) ; 130 MHz setting
xlli_MSC0_136 EQU (0x16B016B0)
xlli_MSC0_143 EQU (0x16C016C0)
xlli_MSC0_149 EQU (0x16C016C0)
xlli_MSC0_156 EQU (0x16C016C0)
xlli_MSC0_162 EQU (0x16C016C0)
xlli_MSC0_169 EQU (0x17D017D0) ; Given that the optimal value would be 13 (RDF), but according to B0 manual, it's different
xlli_MSC0_175 EQU (0x17C017C0)
xlli_MSC0_182 EQU (0x17C017C0)
xlli_MSC0_188 EQU (0x17D017D0)
xlli_MSC0_195 EQU (0x17E017E0)
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