fmdhal_asm.s

来自「该BSP是基于PXA270+WINCE的BSP」· S 代码 · 共 248 行

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; Copyright 2002-2004 Intel Corporation All Rights Reserved.
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   AREA     |.text|, CODE
   ALIGN    4

   EXPORT   FMDHAL_ASM_CallFuncWithNewStack
   EXPORT FMDHAL_ASMInterruptEnable
   EXPORT FMDHAL_ASMInterruptDisable
   
   IMPORT   g_FMDHAL_FuncPtr          ; IMPORTING routine to call
   IMPORT   g_FMDHAL_Stack          ; PSM Global Stack Space created in fmdhal.c
   IMPORT   FMDHAL_OrigStack    ; LOCATION TO STORE ORIG STACK

FMDHAL_ASM_CallFuncWithNewStack

  ;DCD      0xE6000010
  ;DCD      0xE6000010
  ;DCD      0xE6000010
  ;DCD      0xE6000010
  STMFD    SP!, {R1-R12, LR}        ; save the registers onto the stack STMFD


  
   LDR      R3, =FMDHAL_OrigStack    ; save the stack pointer in a global variable r4, [pc, #0x28]
   STR      SP, [R3]                 ; Save stack now in global sp, [r4]
   LDR      R2, =g_FMDHAL_Stack      ; R2 = &PSM_Stack r2, [pc, #0x24]
   ADD      R2, R2, #4096            ; Increment by sizeof(PSM_Stack) r2, r2, #1, 20
   MOV      SP, R2                   ; point stack ptr to [R2] sp, r2
   LDR      R1, =g_FMDHAL_FuncPtr    ; r1, [pc, #0x1C]
   LDR      R0, [R1]                 ; r0, [r1]
   MOV      LR, PC                   ; lr, pc
   MOV      PC, R0                   ; pc, r0
   LDR      R3, =FMDHAL_OrigStack    ; Restore the stack r4, [pc, #4]
   LDR      SP, [R3]                 ; sp, [r4]
   LDMIA    SP!, {R1-R12, PC}        ; Return sp!, {r0 - r12, pc}

 

;******************************************************************************
; "FMDHAL_ASMDisableInterrupts"
;
; Description:
;    Disable all interrupts on the Bulverde processor.  We will disable
;    interrupts by setting the FIQ and IRQ disable bits (5 & 6) to 1's in the
;    Current Program Status Register (CPSR). We will save and restore the bit
;    values later.
;
; Processing:
;    Temp      = CPSR
;    ReturnVal = Temp
;    Temp      = Temp | 0xC0
;    CPSR      = Temp
;    return (ReturnVal)
;
; Inputs:
;    None
;
; Return Value:
;    Contents of the CPSR before modified in R0
;
; Register Usage:
;    R12, R0, CPSR
;       R0 contains the return value from this function.  So we restore the
;       values of all the registers except R0 and return gracefully from this
;       function.
;******************************************************************************
FMDHAL_ASMInterruptDisable
FMDDISMASK EQU   0x000000C0        ; AND mask to extract interrupt settings
   STMFD   SP!,  {R12, LR}
   MRS     R12,  CPSR              ; read the current program status register (cpsr) into R12
   MOV     R0,   R12               ; copy R12 into the return value register
   ORR     R12,  R12, #FMDDISMASK  ; set the IRQ and FIQ mask bits to 1.
   LDMIA   SP!,  {R12, PC}         ; Return


;******************************************************************************
; "FMDHAL_ASMEnableInterrupts"
;
; Description:
;    Enable interrupts on the Bulverde processor.  We will re-enable interrupts
;    by restoring the old values that were found in the CPSR when we disabled
;    interrupts.
;
; Processing:
;    Mask = old_CPSR & 0xC0
;    Temp = CPSR
;    Temp = BitClear(Temp, 0xC0)
;    Temp = Temp | Mask
;    CPSR = Temp
;
; Inputs:
;    Old CPSR before interrupts disabled in R0
;
; Return Value:
;    None
;
; Register Usage:
;    R0, R12, CPSR
;******************************************************************************
FMDHAL_ASMInterruptEnable
FMDINTMASK EQU   0x000000C0       ; AND mask to extract interrupt settings
   STMFD   SP!,  {R0-R12, LR}
   AND     R0,   R0, #FMDINTMASK  ; isolate bits 5 and 6, old interrupt settings
   MRS     R12,  CPSR             ; read the current program status register into R12
   BIC     R12,  R12, #FMDINTMASK ; clear bits 5 and 6 in prep for the OR operation
   ORR     R12,  R12, R0          ; OR in the old values that were in bits 5 and 6
   LDMIA   SP!,  {R0-R12, PC}     ; Return




;------------------------------------------------------------------------
; This macro issues a CPWAIT by using a specific register
;
    MACRO 
    CPWAIT_RX $tag
    
    mrc p15, 0, $tag, c2, c0, 0
    mov $tag, $tag
    sub pc, pc, #4

    MEND
;------------------------------------------------------------------------
; This macro will Clean a given Data Cache line dictated by bits [31:5] of $tag
;        
    MACRO
    CLEAN_DCACHE_LINE $tag
        
    ; Issue clean command
        ;
        mcr p15, 0, $tag, c7, c10, 1

    MEND

;------------------------------------------------------------------------
; This macro will Drain the Wite & Fill Buffers dictated by bits [31:5] of $tag
;        
    MACRO
    DRAIN_BUFFER $tag
        
    ; Issue buffer drain command
        ;
        mcr p15, 0, $tag, c7, c10, 4

    MEND

;------------------------------------------------------------------------
; This macro will Invalidate a given Data Cache line dictated by bits [31:5] of $tag
;        
    MACRO
    INVALIDATE_D_CACHE_LINE $tag
        
    ; Issue invalidate command
        ;
        mcr p15, 0, $tag, c7, c6, 1

    MEND

;------------------------------------------------------------------------
; This macro will Invalidate a given I Cache line dictated by bits [31:5] of $tag
;        
    MACRO
    INVALIDATE_I_CACHE_LINE $tag
        
    ; Issue invalidate command
        ;
        mcr p15, 0, $tag, c7, c5, 1

    MEND

    EXPORT FMD_CleanCacheLine

FMD_CleanCacheLine  
    
     ;Stack all registers
    stmdb r13!,{r0-r12,r14}
    
    ;  unlock data cache - DON'T need to do this right now - have to research
    ; into our future locking plans, we may need to return error here 
    ; in the future 
    ;mcr p15,0,r0,c9,c2,1 
    
    ;   drain: clean the write memory fifo
    DRAIN_BUFFER r0

    ;  Clean the data cache line
    CLEAN_DCACHE_LINE r0  ;  R0: address of the memory region
    CPWAIT_RX r2
    ;   drain: clean the write memory fifo
    DRAIN_BUFFER r0
    CPWAIT_RX r2
    
    ;  unlock the instruction cache:only unlocked lines can be invalidated - 
    ; AGAIN, DON't DO this now, need to research into how we plan on locking
    ; things into the cache which could break this
    ;mcr p15,0,r0,c9,c1,1
    
    ;  invalid the instruction cache
    INVALIDATE_I_CACHE_LINE r0
    CPWAIT_RX r2

    ; Invalidate the BTB - Use r0, as you've just invalidated that instruction
    mcr p15,0, r0, c7,c5,6

    ; At this point the piplene is empty
    ;

    ; Invalide DCACHE line
    ;
    mcr p15,0,R0,c7,c6,1
    CPWAIT_RX r2

    ldmia r13!,{r0-r12,r14}
     
    IF Interworking :LOR: Thumbing
       bx  lr
    ELSE
       mov  pc, lr          ; return
    ENDIF

   END