bsp_cfg.h

来自「该BSP是基于PXA270+WINCE的BSP」· C头文件 代码 · 共 72 行

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for Mainstone II board.
//
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX       "MAINSTN"      // Device name prefix

//------------------------------------------------------------------------------
// Board clock
//------------------------------------------------------------------------------

// OSCR0 is used for the system tick timer.  Use the 3.25MHz clock.
//
#define OEM_CLOCK_FREQ          3250000        // 3.25M ticks/sec
#define OEM_TICKS_1MS           3250           // 1ms in ticks
#define RESCHED_PERIOD          1              // Reschedule period in ms
#define RESCHED_INCREMENT       (RESCHED_PERIOD * OEM_TICKS_1MS)    // Reschedule
                                               // period in ticks
#define OEM_TICK_COUNT_MARGIN   400

//------------------------------------------------------------------------------
// Static SYSINTR Mapping for driver.
#define SYSINTR_OHCI            (SYSINTR_FIRMWARE+1)  // 17
#define SYSINTR_TOUCH           (SYSINTR_FIRMWARE+2)  // 18
#define SYSINTR_TOUCH_CHANGED   (SYSINTR_FIRMWARE+3)  // 19
#define SYSINTR_KEYPAD          (SYSINTR_FIRMWARE+4)  // 20
#define SYSINTR_PCCARD_CSC_S0   (SYSINTR_FIRMWARE+5)  // 21
#define SYSINTR_PCCARD_CD_S0    (SYSINTR_FIRMWARE+6)  // 22
#define SYSINTR_PCCARD_CSC_S1   (SYSINTR_FIRMWARE+7)  // 23	///SBS board has 1 socket,use this irq as NET interrupt
#define SYSINTR_PCCARD_CD_S1    (SYSINTR_FIRMWARE+8)  // 24
#define SYSINTR_AUDIO           (SYSINTR_FIRMWARE+9)  // 25
#define SYSINTR_USBFN           (SYSINTR_FIRMWARE+10) // 26
#define SYSINTR_SFUART          (SYSINTR_FIRMWARE+11) // 27
#define SYSINTR_BFUART          (SYSINTR_FIRMWARE+12) // 28
#define SYSINTR_FFUART          (SYSINTR_FIRMWARE+13) // 29

#define SYSINTR_PWRBTN          (SYSINTR_FIRMWARE+14) // 30
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
#define SYSINTR_LAN91C111		(SYSINTR_FIRMWARE+15) // 31
#define SYSINTR_SD				(SYSINTR_FIRMWARE+16) // 32
//------------------------------------------------------------------------------

// HW switch settings for ARGS
#define CLEAN_BOOT_FLAG  SW20_MASK
#define HIVE_CLEAN_FLAG  SW19_MASK
#define FORMAT_PART_FLAG SW18_MASK
#define UPDATE_MODE_FLAG SW17_MASK

#endif