startup.s

来自「该BSP是基于PXA270+WINCE的BSP」· S 代码 · 共 138 行

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Kernel startup routine for the Intel Mainstone II board.
;
;------------------------------------------------------------------------------

    INCLUDE kxarm.h
    INCLUDE bulverde.inc
    INCLUDE mainstoneii.inc
    INCLUDE xlli_Bulverde_defs.inc
    INCLUDE xlli_Mainstone_defs.inc
    
    IMPORT  KernelStart

    TEXTAREA
       
;------------------------------------------------------------------------
    
     
    ; Include memory configuration file with g_oalAddressTable
    ;
    INCLUDE oemaddrtab_cfg.inc
 
;-------------------------------------------------------------------------------
;
; OALStartUp: OEM OAL startup code.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0
;
;-------------------------------------------------------------------------------
;
    ALIGN
    LEAF_ENTRY OALStartUp

    ; Initialize the hex LEDs on the Mainstone II board.  These use GPIOs which were
    ; configured in the OALXScaleSetFrequencies callback during clock initialization.
    ;
    bl      Init_HexLEDs
    
    ; Compute the OEMAddressTable's physical address and 
    ; load it into r0. KernelStart expects r0 to contain
    ; the physical address of this table. The MMU isn't 
    ; turned on until well into KernelStart.  
    ;
    add     r0, pc, #g_oalAddressTable - (. + 8)
    mov     r11, r0
    b       KernelStart
    nop
    nop
    nop
    nop
    nop
    nop
    
STALL
    b       STALL               ; Spin forever.


;-------------------------------------------------------------------------------
;
; Init_HexLEDs: Initializes the Mainstone II board logic to enable the hex LEDs.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0-r3
;
;-------------------------------------------------------------------------------
;
    ALIGN
Init_HexLEDs

    ldr     r3, =BULVERDE_BASE_REG_PA_MEMC
    ldr     r2, =xlli_MSC1_value
    str     r2, [r3, #xlli_MSC1_offset]       ; Need to set MSC1 before trying to write to the HEX LEDs
    ldr     r2, [r3, #xlli_MSC1_offset]       ; Need to read it back to make sure the value latches (see MSC section of manual)

    ldr     r1, =MAINSTONEII_BASE_REG_PA_FPGA
    mov     r0, #0x0
    str     r0, [r1, #LEDCTL_OFFSET]          ; Blank hex & discrete leds
;------------------------------
;    setHexLED   r1, r0
;------------------------------
  IF Interworking :LOR: Thumbing
    bx       lr
  ELSE
    mov      pc, lr                           ; Return to caller.
  ENDIF



;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------

    LTORG                           ; insert a literal pool here.

;
; TURN_ON_BTB - Enables the Branch Target Buffer
;
; Turn on the BTB via cp15.1[11] - Uses r0
;
;
    LEAF_ENTRY TURN_ON_BTB

    mcr p15, 0, r0, c7, c5, 0   ; flush the icache & BTB
    mrc p15, 0, r0, c1, c0, 0
    orr r0, r0, #0x800
    mcr p15, 0, r0, c1, c0, 0

  IF Interworking :LOR: Thumbing
    bx  lr
  ELSE
    mov  pc, lr          ; return
  ENDIF
   
        
    END 

;------------------------------------------------------------------------------