intr.c

来自「该BSP是基于PXA270+WINCE的BSP」· C语言 代码 · 共 552 行 · 第 1/2 页

	}
//--------------------------------------------------------------


//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO24)	{
		RETAILMSG(1, (TEXT("BSPIntrDisableIrq-->IRQ_GPIOXX_2_GPIO24-------\r\n")));
		g_pGPIORegs->GRER0 &= ~XLLP_BIT_24;
		g_pGPIORegs->GFER0 &= ~XLLP_BIT_24;
	}
//--------------------------------------------------------------

//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO81)	{
		RETAILMSG(1, (TEXT("BSPIntrDisableIrq-->IRQ_GPIOXX_2_GPIO81-------\r\n")));
		g_pGPIORegs->GRER2 &= ~XLLP_BIT_17;
		g_pGPIORegs->GEDR2 = XLLP_BIT_17;	//test wzw
	}
//--------------------------------------------------------------

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDisableIrq(irq = %d\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDoneIrq
//
//  This function is called from OALIntrDoneIrq to finish interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDoneIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDoneIrq(%d)\r\n", irq));

    // Valid board-level interrupt?
    if (g_pBLRegs && (irq >= IRQ_MAINSTONEII_GPIO0_MIN) && (irq <= IRQ_MAINSTONEII_GPIO0_MAX))
    {
        UINT32 TempVal;
        TempVal = INREG32((PULONG)&g_pBLRegs->int_set_clr) & ~INTSETCLR_RESERVED_BITS;
        OUTREG32((PULONG)&g_pBLRegs->int_set_clr, (TempVal & ~FPGA_INT_BIT(irq)));

        TempVal = (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);
        OUTREG32((PULONG)&g_pBLRegs->int_msk_en, (TempVal | FPGA_INT_BIT(irq)));

        // Masking the interrupt at the FPGA controller is enough - no need to mask the Bulverde GPIO0 interrupt.
        irq = OAL_INTR_IRQ_UNDEFINED;
    }

//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO11)	{
		g_pGPIORegs->GRER0 |= XLLP_BIT_11;
//		g_pGPIORegs->GEDR0  = XLLP_BIT_11;//+
	}
//--------------------------------------------------------------


//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO24)	{
		g_pGPIORegs->GRER0 |= XLLP_BIT_24;
		g_pGPIORegs->GFER0 |= XLLP_BIT_24;
//		g_pGPIORegs->GEDR0  = XLLP_BIT_24;//+
	}
//--------------------------------------------------------------

//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO81)	{
		g_pGPIORegs->GRER2 |= XLLP_BIT_17;

	}

//	if(irq == IRQ_OSMR1)	{
//		g_pGPIORegs->GRER2 |= XLLP_BIT_17;
//		g_pGPIORegs->GEDR2  = XLLP_BIT_17;
//	}

//#define GEDR_GPIO81_EDGE_CLR(reg) 	(reg = XLLP_BIT_17)	
//GEDR_GPIO81_EDGE_EN(v_pGPIOReg->GRER2);
//GEDR_GPIO81_EDGE_CLR(v_pGPIOReg->GEDR2);
//--------------------------------------------------------------

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDoneIrq(irq = %d)\r\n", irq));
    return irq;
}


//------------------------------------------------------------------------------
//
//  Function:  BSPIntrActiveIrq
//
//  This function is called from interrupt handler to give BSP chance to 
//  translate IRQ in case of secondary interrupt controller.
//
UINT32 BSPIntrActiveIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrActiveIrq(%d)\r\n", irq));

//	RETAILMSG(1, (TEXT("BSPIntrActiveIrq ------------\r\n")));///+

    switch(irq)
    {
    case IRQ_GPIO0:
//-----------------------------
      irq = FPGAInterruptHandler(irq);
//-----------------------------
        break;

    case IRQ_GPIO1:
        ClearGPIO1Irq();
        break;

    case IRQ_GPIOXX_2:

//---------------------------
		if (g_pGPIORegs->GEDR1 & (1u << 20) ) 	{
//			RETAILMSG(1, (TEXT("BSPIntrActiveIrq-->IRQ_GPIOXX_2_GPIO52------\r\n")));
            g_pGPIORegs->GRER1 &= ~XLLP_BIT_20;//+
			g_pGPIORegs->GEDR1 |= (1u << 20);  	//write 1 to clear
			irq = IRQ_GPIOXX_2_GPIO52;		
		}
//---------------------------
//--------------------------------------------------------------
		if (g_pGPIORegs->GEDR0 & (1u << 11) ) 	{
//			RETAILMSG(1, (TEXT("BSPIntrActiveIrq-->IRQ_GPIOXX_2_GPIO11------\r\n")));//y
            g_pGPIORegs->GRER0 &= ~XLLP_BIT_11;//+
            g_pGPIORegs->GEDR0 = XLLP_BIT_11;
            irq = IRQ_GPIOXX_2_GPIO11;
		}
//--------------------------------------------------------------		

//--------------------------------------------------------------
		if (g_pGPIORegs->GEDR0 & (1u << 24) ) 	{
			RETAILMSG(1, (TEXT("BSPIntrActiveIrq-->IRQ_GPIOXX_2_GPIO24------\r\n")));//y
            g_pGPIORegs->GRER0 &= ~XLLP_BIT_24;//+
            g_pGPIORegs->GEDR0 = XLLP_BIT_24;
            irq = IRQ_GPIOXX_2_GPIO24;
		}
//--------------------------------------------------------------		

//--------------------------------------------------------------
		if (g_pGPIORegs->GEDR2 & (1u << 17) ) 	{
//			RETAILMSG(1, (TEXT("BSPIntrActiveIrq-->IRQ_GPIOXX_2_GPIO81------\r\n")));//
            g_pGPIORegs->GRER2 &= ~XLLP_BIT_17;
            g_pGPIORegs->GEDR2 = XLLP_BIT_17;
            irq = IRQ_GPIOXX_2_GPIO81;
		}
//--------------------------------------------------------------

        break;	


//--------------------------------------------------------------
//    case IRQ_OSMR1:
//		RETAILMSG(1, (TEXT("BSPIntrActiveIrq-->IRQ_OSMR1---@@@@-->>>>>>>>>>>>>>>>>>-\r\n")));//
//		irq = OAL_INTR_IRQ_UNDEFINED;
//   	    break;
//--------------------------------------------------------------

    default:
        break;
    }

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrActiveIrq(%d)\r\n", irq));
    return irq;
}


//------------------------------------------------------------------------------
//
//  Function:  FPGAInterruptHandler
//
//  This function is called from the BSP ISR to handle an FPGA interrupt.
//
static UINT32 FPGAInterruptHandler(UINT32 irq)
{
    UINT8  nInt;
    UINT32 TempVal;

	RETAILMSG(1, (TEXT("FPGAInterruptHandler ------------\r\n")));///+

    // Read the pending FPGA interrupts and ignore masked/reserved interrupts.
    TempVal  = INREG32((PULONG)&g_pBLRegs->int_set_clr);
    TempVal &= (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);

    // Scan through the pending interrupts and look for a match.
    for (nInt = IRQ_MAINSTONEII_GPIO0_MIN ; nInt <= IRQ_MAINSTONEII_GPIO0_MAX ; nInt++)
    {
        if (TempVal & FPGA_INT_BIT(nInt))
        {	
            // Mask and clear the interrupt (note that we must write 0's to the reserved bits).
            // Interrupt acknowledge occurs in the SMC ISR routine
            TempVal = INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS;
            OUTREG32((PULONG)&g_pBLRegs->int_msk_en,  (TempVal & ~FPGA_INT_BIT(nInt)));

            TempVal = INREG32((PULONG)&g_pBLRegs->int_set_clr) & ~INTSETCLR_RESERVED_BITS;
            OUTREG32((PULONG)&g_pBLRegs->int_set_clr, (TempVal & ~FPGA_INT_BIT(nInt)));

            break;
        }
    }

    // If we see the PCCARD client IRQ asserted, look to see if the card is present in the
    // slot.  The MainstoneII PCCARD FPGA implementation is asserting the client IRQ upon
    // card removal which can cause problems down the line when we try to read from the card.
    //
    if (nInt == IRQ_GPIO0_PCMCIA_S0)
    {
        if (g_pBLRegs->pcmcia0_srcr & PCMCIA_S0_nCD_MASK) nInt = IRQ_GPIO0;
    }
    if (nInt == IRQ_GPIO0_PCMCIA_S1)
    {
        if (g_pBLRegs->pcmcia1_srcr & PCMCIA_S1_nCD_MASK) nInt = IRQ_GPIO0;
    }

    // *** The following is to work around a problem in the MainstoneII FPGA ***
    //
    // Bulverde requires a minimum GPIO0 deassertion period before the GPIO0
    // signal can be reasserted.  Failure to comply can lead to problems with 
    // GPIO0 interrupt detection.  As well, because the FPGA interrupt masking
    // operation is a non-atomic read-modify-write operation, it's possible
    // that an async FPGA interrupt can assert during that sequence which
    // in turn violates Bulverde's GPIO0 timing requirements.
    //

    // 1.  First, we'll save off the current interrupt mask (it will be later restored).
    TempVal = (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);

    // 2.  Disable all FPGA interrupts (disable FPGA GPIO0 assertion to Bulverde).
    OUTREG32((PULONG)&g_pBLRegs->int_msk_en,  0);

    // 3.  Clear the Bulverde GPIO0 falling edge detection.
    OUTREG32((PULONG)&g_pGPIORegs->GEDR0, XLLP_GPIO_BIT_0);

    // 4.  Wait...
    OALStall(1);

    // 5.  Restore the FPGA mask (this will cause any pending interrupts to assert
    //     to the Bulverde).
    OUTREG32((PULONG)&g_pBLRegs->int_msk_en,  TempVal);

    return((nInt <= IRQ_MAINSTONEII_GPIO0_MAX) ? nInt : irq);
}

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//  Function:  Enables the GPIO1 Irq by setting the corresponding GFERx and GRERx bits
//
static void EnableGPIO1Irq(void)
{
//	RETAILMSG(1, (TEXT("EnableGPIO1Irq ------------\r\n")));///+
    SETREG32((PULONG)&g_pGPIORegs->GFER0, XLLP_GPIO_BIT_1);
    SETREG32((PULONG)&g_pGPIORegs->GRER0, XLLP_GPIO_BIT_1);
}

//------------------------------------------------------------------------------
//
//  Function:  disables the GPIO1 Irq by clearing the corresponding GFERx and GRERx bits
//
static void DisableGPIO1Irq(void)
{
	RETAILMSG(1, (TEXT("DisableGPIO1Irq ------------\r\n")));///+
    CLRREG32((PULONG)&g_pGPIORegs->GFER0, XLLP_GPIO_BIT_1);
    CLRREG32((PULONG)&g_pGPIORegs->GRER0, XLLP_GPIO_BIT_1);
}

//------------------------------------------------------------------------------
//
//  Function:  clears the GPIO1 Irq by clearing the GEDRx bit
//
static void ClearGPIO1Irq(void)
{
    g_pGPIORegs->GEDR0 = XLLP_GPIO_BIT_1;
}