intr.c

来自「该BSP是基于PXA270+WINCE的BSP」· C语言 代码 · 共 552 行 · 第 1/2 页

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  intr.h
//
//  This file contains MainstoneII board specific interrupt code.
//
#include <bsp.h>
#include <intr_fpga.h>

static UINT32 FPGAInterruptHandler(UINT32 ra);
static void EnableGPIO1Irq(void);
static void DisableGPIO1Irq(void);
static void ClearGPIO1Irq(void);

static volatile MAINSTONEII_BLR_REGS *g_pBLRegs = NULL;
static volatile BULVERDE_GPIO_REG    *g_pGPIORegs = NULL;

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrInit
//
BOOL BSPIntrInit()
{
    volatile BULVERDE_INTR_REG *pIntrRegs = NULL;

    OALMSG(OAL_INTR&&OAL_FUNC, (L"+BSPIntrInit\r\n"));

    pIntrRegs   = (volatile BULVERDE_INTR_REG *) OALPAtoVA(BULVERDE_BASE_REG_PA_INTC, FALSE);
    g_pBLRegs   = (volatile MAINSTONEII_BLR_REGS *) OALPAtoVA(MAINSTONEII_BASE_REG_PA_FPGA, FALSE);
    g_pGPIORegs = (volatile BULVERDE_GPIO_REG *) OALPAtoVA(BULVERDE_BASE_REG_PA_GPIO, FALSE);

//-----------------------------------------------------------------
	g_pGPIORegs->GPDR1 &= ~(1u <<20);	//0==input.GPIO52

	g_pGPIORegs->GPDR0 &= ~(1u <<11);	//0==input.GPIO11
	g_pGPIORegs->GAFR0_L &= ~(3u <<22);	//0==GPIO.GPIO11

	g_pGPIORegs->GPDR0 &= ~(1u <<24);	//0==input.GPIO24
	g_pGPIORegs->GAFR0_U &= ~(3u <<16);	//0==GPIO.GPIO24

	g_pGPIORegs->GPDR2 &= ~(1u <<17);	//0==input.GPIO81
	g_pGPIORegs->GAFR2_U &= ~(3u <<2);	//0==GPIO.GPIO81
//-----------------------------------------------------------------
    // Mask and clear all FPGA interrupts.
    //
    g_pBLRegs->int_msk_en  = 0;
    g_pBLRegs->int_set_clr = 0;

//------------------------------------------------
    // Enable USB Cable detection interrupts
    OUTREG32((PULONG)&g_pBLRegs->int_msk_en, FPGA_INT_BIT(IRQ_GPIO0_USBCD));
//------------------------------------------------


//-----------------------------------------------------------------------
    // Enable GPIO 0 for falling edge (Active Low) to signal the FPGA interrupts.
//    SETREG32((PULONG)&g_pGPIORegs->GFER0, XLLP_GPIO_BIT_0);
//    SETREG32((PULONG)&pIntrRegs->icmr, (1 << IRQ_GPIO0));
//-----------------------------------------------------------------------

    // Set up static interrupt mappings
//-----------------------------------------------------------------------
    // Enable GPIO 2-118 Interrupt
    SETREG32((PULONG)&pIntrRegs->icmr, (1 << IRQ_GPIOXX_2));//#
    OALIntrStaticTranslate(SYSINTR_LAN91C111, IRQ_GPIOXX_2_GPIO11);//dm9000 actually,here just a name
//-----------------------------------------------------------------------	
    OALIntrStaticTranslate(SYSINTR_OHCI, IRQ_USBOHCI);

//-----------------------------------------------------------------------
//  OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIO0_UCB1400);
    OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIOXX_2_GPIO81);
//-----------------------------------------------------------------------
    OALIntrStaticTranslate(SYSINTR_TOUCH_CHANGED, IRQ_OSMR1);
    OALIntrStaticTranslate(SYSINTR_KEYPAD, IRQ_KEYPAD);

    OALIntrStaticTranslate(SYSINTR_FFUART, IRQ_FFUART);
    OALIntrStaticTranslate(SYSINTR_BFUART, IRQ_BTUART);
    OALIntrStaticTranslate(SYSINTR_SFUART, IRQ_STUART);

//-----------------------------------------------------------------------
//    OALIntrStaticTranslate(SYSINTR_PCCARD_CSC_S0, IRQ_GPIO0_PCMCIA_S0_CSC);
//    OALIntrStaticTranslate(SYSINTR_PCCARD_CD_S0, IRQ_GPIO0_PCMCIA_S0_CD);	/// 73, 0x49
//    OALIntrStaticTranslate(SYSINTR_PCCARD_CSC_S1, IRQ_GPIO0_PCMCIA_S1_CSC);
//    OALIntrStaticTranslate(SYSINTR_PCCARD_CD_S1, IRQ_GPIO0_PCMCIA_S1_CD);
//-----------------------------------------------------------------------
    OALIntrStaticTranslate(SYSINTR_PCCARD_CSC_S0, IRQ_GPIOXX_2_GPIO52);
//-----------------------------------------------------------------------

//-----------------------------------------------------------------------
//    OALIntrStaticTranslate(SYSINTR_SD, IRQ_GPIOXX_2_GPIO24);	//122=0x7A
//-----------------------------------------------------------------------


    OALIntrStaticTranslate(SYSINTR_AUDIO, IRQ_DMAC);

    OALIntrStaticTranslate(SYSINTR_USBFN, IRQ_USBFN);

    OALIntrStaticTranslate(SYSINTR_PWRBTN, IRQ_GPIO1);

    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrInit\r\n"));

    return TRUE;
}

//------------------------------------------------------------------------------

BOOL BSPIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
    BOOL rc = FALSE;

	RETAILMSG(1, (TEXT("BSPIntrRequestIrqs ------------\r\n")));///+

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+BSPIntrRequestIrq(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n", 
        pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
        pDevLoc->Pin, pCount, pIrqs
    ));

    // Check for input params
    if (pIrqs == NULL || pCount == NULL || *pCount < 1) goto Done;

    switch (pDevLoc->IfcType) {
    case Internal:
        switch ((ULONG)pDevLoc->LogicalLoc) {
//----------------
//      case (MAINSTONEII_BASE_REG_PA_SMSC_ETHERNET + 0x300):
        case (MAINSTONEII_BASE_REG_PA_SMSC_ETHERNET):	///?????
			RETAILMSG(1, (TEXT("BSPIntrRequestIrqs   IRQ_GPIO0_ETHERNET ------------\r\n")));
//----------------
//------------------------------
//          pIrqs[0] = IRQ_GPIO0_ETHERNET;
            pIrqs[0] = IRQ_GPIOXX_2_GPIO11;
//------------------------------	
            *pCount = 1;
            rc = TRUE;
            break;
        }
        break;
    }

Done:
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrRequestIrq(rc = %d)\r\n", rc));
    return rc;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrEnableIrq
//
//  This function is called from OALIntrEnableIrq to enable interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrEnableIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrEnableIrq(%d)\r\n", irq));

//	RETAILMSG(1, (TEXT("BSPIntrEnableIrq ------------\r\n")));///+y

    // Valid board-level interrupt?
    if (g_pBLRegs && (irq >= IRQ_MAINSTONEII_GPIO0_MIN) && (irq <= IRQ_MAINSTONEII_GPIO0_MAX))
    {

//------------------------------------------------
        UINT32 TempVal = (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);

        OUTREG32((PULONG)&g_pBLRegs->int_msk_en, (TempVal | FPGA_INT_BIT(irq)));

//		RETAILMSG(1, (TEXT("IRQ_MAINSTONEII_GPIO0 enable ------------# %d\r\n"),irq)); 
//------------------------------------------------

        // Enabling the interrupt at the FPGA controller is enough - no need to enable the Bulverde GPIO0 interrupt.
        irq = OAL_INTR_IRQ_UNDEFINED;
    }
    else if(irq == IRQ_GPIO1)
    {
//		RETAILMSG(1, (TEXT("IRQ_GPIO1 enable ------------\r\n")));    
        EnableGPIO1Irq();
    }


//-----------------------------------------------
	else if(irq == IRQ_GPIOXX_2_GPIO52)	{
//		RETAILMSG(1, (TEXT("BSPIntrEnableIrq-->IRQ_GPIOXX_2_GPIO52---------\r\n")));
		g_pGPIORegs->GRER1 |= (1u <<20);	//1==enable.GPIO52
		g_pGPIORegs->GFER1 |= (1u <<20);	//1==enable.GPIO52
	}
//-----------------------------------------------

//-----------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO11)	{
//		RETAILMSG(1, (TEXT("BSPIntrEnableIrq-->IRQ_GPIOXX_2_GPIO11---------\r\n")));
		g_pGPIORegs->GRER0 |= XLLP_BIT_11;
	}
//-----------------------------------------------			


//-----------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO24)	{
//		RETAILMSG(1, (TEXT("BSPIntrEnableIrq-->IRQ_GPIOXX_2_GPIO24---------\r\n")));
		g_pGPIORegs->GRER0 |= XLLP_BIT_24;
		g_pGPIORegs->GFER0 |= XLLP_BIT_24;//+
	}
//-----------------------------------------------			

//-----------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO81)	{
//		RETAILMSG(1, (TEXT("BSPIntrEnableIrq-->IRQ_GPIOXX_2_GPIO81---------\r\n")));
		g_pGPIORegs->GRER2 |= XLLP_BIT_17;

	}

//	if(irq == IRQ_OSMR1)	{
//		RETAILMSG(1, (TEXT("BSPIntrEnableIrq-->IRQ_OSMR1---------\r\n")));
//		g_pGPIORegs->GRER2 |= XLLP_BIT_17;
//	}
//-----------------------------------------------			

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrEnableIrq(irq = %d)\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDisableIrq
//
//  This function is called from OALIntrDisableIrq to disable interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDisableIrq(UINT32 irq)
{
UINT32 TempVal;

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDisableIrq(%d)\r\n", irq));

//	RETAILMSG(1, (TEXT("BSPIntrDisableIrq ------------\r\n")));///+

    // Valid board-level interrupt?
    if (g_pBLRegs && (irq >= IRQ_MAINSTONEII_GPIO0_MIN) && (irq <= IRQ_MAINSTONEII_GPIO0_MAX))
    {
//      UINT32 TempVal = (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);
               TempVal = (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);
		
        OUTREG32((PULONG)&g_pBLRegs->int_msk_en, (TempVal & ~FPGA_INT_BIT(irq)));

        // Masking the interrupt at the FPGA controller is enough - no need to mask the Bulverde GPIO0 interrupt.
        irq = OAL_INTR_IRQ_UNDEFINED;
    }
    else if(irq == IRQ_GPIO1)
    {
        DisableGPIO1Irq();
    }


//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO52)	{
//		RETAILMSG(1, (TEXT("BSPIntrDisableIrq-->IRQ_GPIOXX_2_GPIO52-------\r\n")));
		g_pGPIORegs->GRER1 &= ~(1u <<20);	//1==enable.GPIO52
		g_pGPIORegs->GFER1 &= ~(1u <<20);	//1==enable.GPIO52
	}
//--------------------------------------------------------------

//--------------------------------------------------------------
	if(irq == IRQ_GPIOXX_2_GPIO11)	{
//		RETAILMSG(1, (TEXT("BSPIntrDisableIrq-->IRQ_GPIOXX_2_GPIO11-------\r\n")));
		g_pGPIORegs->GRER0 &= ~XLLP_BIT_11;
		g_pGPIORegs->GEDR0 = XLLP_BIT_11;	//>>>