startup.s

来自「该BSP是基于PXA270+WINCE的BSP」· S 代码 · 共 179 行

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;

    INCLUDE kxarm.h
    INCLUDE bulverde.inc
    INCLUDE mainstoneii.inc
    INCLUDE image_cfg.inc
    
    INCLUDE xlli_Bulverde_defs.inc
    INCLUDE xlli_Mainstone_defs.inc
   
    
    TEXTAREA

    IMPORT	main
    IMPORT OALVAtoPA
    IMPORT OALPAtoVA

    ; Included within the text section in order that a relative offset can be
    ; computed in the code below.
    ;
    INCLUDE oemaddrtab_cfg.inc

;-------------------------------------------------------------------------------
;
; OALStartUp: OEM bootloader startup code.  This routine will:
;
; * Copy the image to RAM if it's not already running there.
;
; * Initialize the first-level page table based up the contents
;   of the MemoryMap array and enable the MMU and caches.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used:
;
;-------------------------------------------------------------------------------
;
    ALIGN
    
    LEAF_ENTRY OALStartUp

    ; Initialize the hex LEDs on the Mainstone II board.  These use GPIOs which were
    ; configured in the OALXScaleSetFrequencies callback during clock initialization.
    ;
    bl      Init_HexLEDs

    ; Copy the bootloader image from flash to RAM.  The image is configured
    ; to run in RAM, but is stored in flash.  Absolute address references
    ; should be avoided until the image has been relocated and the MMU enabled.
    ;
    ; TODO - check to see if the PC is already in RAM.
    ;
    ; NOTE: The destination (RAM) address must match the address in the
    ; IPL's .bib file.  The latter dictates the code fix-up addresses.
    ;
    ldr     r8, =IMAGE_BOOT_IPL_FLASH_PA_START     ; IPL is stored near the base of the boot flash.
                                                   ; Bootloader is fixed up to run in SDRAM (this value
                                                   ; must match the NK start address in the .bib file).
    ldr     r1, =IMAGE_BOOT_IPL_RAM_PA_START
    ldr     r2, =(IMAGE_BOOT_IPL_FLASH_MAXSIZE / 16)    ; IPL image length (this must be <= the NK
                                                        ; length in the .bib file).  We are block-copying 
                                                        ; 16-bytes per iteration.
                                                   
    ; Do 4x32-bit block copies from flash->RAM (corrupts r4-r7).
    ;
10  ldmia   r8!, {r4-r7}        ; Loads from flash (post increment).
    stmia   r1!, {r4-r7}        ; Stores to RAM (post increment).
    subs    r2, r2, #1          ;
    bne     %B10                ; Done?

    ; Verify that the copy succeeded by comparing the flash and RAM contents.
    ;
    ldr     r0, =IMAGE_BOOT_IPL_FLASH_MAXSIZE
    ldr     r1, =IMAGE_BOOT_IPL_RAM_PA_START
    ldr     r2, =IMAGE_BOOT_IPL_FLASH_PA_START

VERIFY_LOOP
    ldr     r3, [r1], #4        ; Read longword from DRAM.
    ldr     r4, [r2], #4        ; Read longword from flash.
    cmp     r3, r4              ; Compare.
    bne     VERIFY_FAILURE      ; Not the same? Fail.
    subs    r0, r0, #4          ;
    bne     VERIFY_LOOP         ; Continue?
    b       VERIFY_DONE         ; Done (success).

VERIFY_FAILURE
    ldr     r0, =MAINSTONEII_BASE_REG_PA_FPGA
    sub     r1, r1, #4          ; Bad RAM address.
    setHexLED  r0, r1           ; Display address.
STALL1
    b       STALL1              ; Spin forever.

VERIFY_DONE

    ; Now that we've copied ourselves to RAM, jump to the RAM image.  Use the "CodeInRAM" label
    ; to determine the RAM-based code address to which we should jump.
    ;
    add     r2, pc, #CODEINRAM-(.+8)          ; Calculate the relative offset to the 'CodeInRAM' label.
    sub     r2, r2, #IMAGE_BOOT_IPL_FLASH_PA_START    ; Adjust for IPL flash offset.
    ldr     r1, =IMAGE_BOOT_IPL_RAM_PA_START    ; Get the RAM address to which we copied ourself.
    add     r1, r1, r2                        ; Calculate the RAM address of the 'CodeInRAM' label.
    mov     pc, r1                            ;
    nop
    nop
    nop

CODEINRAM

    ; We're now running out of RAM.
    ; 
    ldr     r0, =MAINSTONEII_BASE_REG_PA_FPGA
    mov     r1, pc              ; Get the RAM-based PC.
    setHexLED  r0, r1           ; Display it.

    ;  Set up a supervisor mode stack.
    ;
    ; NOTE: These values must match the OEMAddressTable and .bib file entries for
    ; the bootloader.
    ;
    ldr     sp, =IMAGE_BOOT_STACK_RAM_PA_START

    ; Jump to the C entrypoint.
    ;
    bl      main                              ; Jump to main.c::main(), never to return...
    nop
    nop
    nop
    
STALL2
    b      STALL2 



;-------------------------------------------------------------------------------
;
; Init_HexLEDs: Initializes the Mainstone II board logic to enable the hex LEDs.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0-r3
;
;-------------------------------------------------------------------------------
;
    ALIGN
Init_HexLEDs

    ldr     r3, =BULVERDE_BASE_REG_PA_MEMC
    ldr     r2, =xlli_MSC1_value
    str     r2, [r3, #xlli_MSC1_offset]       ; Need to set MSC1 before trying to write to the HEX LEDs
    ldr     r2, [r3, #xlli_MSC1_offset]       ; Need to read it back to make sure the value latches (see MSC section of manual)

    ldr     r1, =MAINSTONEII_BASE_REG_PA_FPGA
    mov     r0, #0x0
    str     r0, [r1, #LEDCTL_OFFSET]          ; Blank hex & discrete leds
    setHexLED   r1, r0

  IF Interworking :LOR: Thumbing
    bx      lr
  ELSE
    mov     pc, lr                            ; Return to caller.
  ENDIF

    END