deskew.vhd

本代码用于路由器的线路接口卡中

                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 
			      
         WHEN INC1_WAIT3 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 

	    -- Check to see if the Q1 output of the ISERDES has changed 
	    -- indicating the first edge has been found.			      
         WHEN EDGE1 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';  
			   
	    -- If the first edge has been found, continue incrememnting 
	    -- the tap delay line while incrementing the tap counter
	    -- until the second edge is found. 			     
         WHEN INC2 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '1';    
                  dlyce_int <= '1';    
                  dlyinc_int <= '1';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 
			      
         WHEN INC2_WAIT1 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';  
			     
         WHEN INC2_WAIT2 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';  
			     
         WHEN INC2_WAIT3 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 

	    -- Check to see if the Q2 output of the ISERDES has changed 
	    -- indicating the second edge has been found.			      
         WHEN EDGE2 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';  
			      
         WHEN EDGE2_WAIT1 =>
                  cnt_rst <= '1';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '1';    
                  done_int <= '0';  

	    -- Once second edge is found, decrement the tap delay line to half
	    -- the value of the tap counter 			     
         WHEN CENTER_DEC =>
                  cnt_rst <= '0';    
                  cnt_inc <= '1';    
                  dlyce_int <= '1';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 

	    -- Check to see if the center point of the data eye has been reached.			      
         WHEN CHECK_CENTER =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';  
			     
         WHEN DESKEW_DONE =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '1'; 
			      
         WHEN DONE_WAIT1 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';   
			    
         WHEN DONE_WAIT2 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 
			     
         WHEN OTHERS  =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';    
         
      END CASE;
   END PROCESS;

   PROCESS (Current_State, rst, deskew_en, counter, edgei_int, edgei_init, center)
   BEGIN                                      
		  CASE Current_State IS
		       WHEN START =>
                  IF (rst = '1') THEN
                     Next_State <= START;    
                  ELSIF (deskew_en = '0') THEN
                     Next_State <= START;    
                  ELSE
                     Next_State <= START_WAIT1;    
                  END IF;
	    -- Insert wait states after START to account for pipeline stages
	    -- in channel select MUX.
             WHEN START_WAIT1 =>
                  Next_State <= START_WAIT2;  
			     
             WHEN START_WAIT2 =>
                  Next_State <= SEEK_EDGE; 
			      
             WHEN SEEK_EDGE =>
                  IF ((((edgei_int(6) OR edgei_int(5)) OR edgei_int(4)) OR edgei_int(3)) = '1') THEN
                     Next_State <= INC1;  				   
                  ELSE
                     Next_State <= SEEK_EDGE;    
                     
                  END IF;

	    -- Increment tap delay line until next left edge is found (edge pattern
	    -- shifts right by one)
             WHEN INC1 =>
                  Next_State <= INC1_WAIT1; 
			      
             WHEN INC1_WAIT1 =>
                  Next_State <= INC1_WAIT2;  	  
		 

             WHEN INC1_WAIT2 =>
                  Next_State <= INC1_WAIT3; 
	     			      
             WHEN INC1_WAIT3 =>
                  Next_State <= EDGE1;   

	    -- Check to see if the Q1 output of the ISERDES has changed 
	    -- indicating the first edge has been found.			    
             WHEN EDGE1 =>
                  IF (edgei_int = STD_LOGIC_VECTOR(UNSIGNED(edgei_init) SRL 1)) THEN
                     Next_State <= INC2;    
                  ELSE
                     Next_State <= INC1;    
                  END IF;

             WHEN INC2 =>
                  Next_State <= INC2_WAIT1; 
			      
             WHEN INC2_WAIT1 =>
                  Next_State <= INC2_WAIT2;
			       
             WHEN INC2_WAIT2 =>
                  Next_State <= INC2_WAIT3;
			       
             WHEN INC2_WAIT3 =>
                  Next_State <= EDGE2; 

	    -- Check to see if the Q2 output of the ISERDES has changed 
	    -- indicating the second edge has been found.			      
             WHEN EDGE2 =>
                  IF (edgei_int = STD_LOGIC_VECTOR(UNSIGNED(edgei_init) SRL 2)) THEN
                     Next_State <= EDGE2_WAIT1;    
                  ELSE
                     Next_State <= INC2;    
                  END IF;

             WHEN EDGE2_WAIT1 =>
                  Next_State <= CENTER_DEC; 

	    -- Once second edge is found, decrement the tap delay line to half
	    -- the value of the tap counter 			      
             WHEN CENTER_DEC =>
                  Next_State <= CHECK_CENTER;  
			     
             WHEN CHECK_CENTER =>
                  IF (counter = center) THEN
                     Next_State <= DESKEW_DONE;    
                  ELSE
                     Next_State <= CENTER_DEC;    
                  END IF;

	    -- Check to see if the center point of the data eye has been reached.
             WHEN DESKEW_DONE =>
                  Next_State <= DONE_WAIT1; 
			      
             WHEN DONE_WAIT1 =>
                  Next_State <= DONE_WAIT2; 
			      
             WHEN DONE_WAIT2 =>
                  Next_State <= START;  
			     
             WHEN OTHERS  =>
                  Next_State <= START;             
         END CASE;
   END PROCESS;

END deskew_arch;