deskew.vhd

本代码用于路由器的线路接口卡中

--********************************************************************
--
--  NDSC. 2006.10.25                
--
--
--*******************************************************************************
--
--  File name :       deskew.vhd (THE DPA FOR A DATA CHANNAL)
--
--  Description :     This module is the deskew module for the DPA design
-- 
--                    
--  Date - revision : --/--/2006
--
--  Author :          WANWEI  HUANG
--
--  Contact : e-mail  [e-mail]
--            phone   + 086 0371 63532770 
--
--  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are provided to
--              you "as is". NDSC and its licensors make and you 
--              receive no warranties or conditions, express, implied, 
--              statutory or otherwise, and NDSC specifically disclaims any 
--              implied warranties of merchantability, non-infringement, or 
--              fitness for a particular purpose. NDSC does not warrant that 
--              the functions contained in these designs will meet your 
--              requirements, or that the operation of these designs will be 
--              uninterrupted or error free, or that defects in the Designs 
--              will be corrected. Furthermore, NDSC does not warrant or 
--              make any representations regarding use or the results of the 
--              use of the designs in terms of correctness, accuracy, 
--              reliability, or otherwise. 
--
--              LIMITATION OF LIABILITY. In no event will NDSC or its 
--              licensors be liable for any loss of data, lost profits, cost 
--              or procurement of substitute goods or services, or for any 
--              special, incidental, consequential, or indirect damages 
--              arising from the use or operation of the designs or 
--              accompanying documentation, however caused and on any theory 
--              of liability. This limitation will apply even if Xilinx 
--              has been advised of the possibility of such damage. This 
--              limitation shall apply not-withstanding the failure of the 
--              essential purpose of any limited remedies herein. 
--
--  Copyright ? 2006 NDSC
--  All rights reserved 
-- 
--*****************************************************************************
---------------------------------------------------------------该模块用于实现数据位的位间调整，使时钟边沿位于数据窗的中心位置------------------

library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.Std_logic_arith.all;
use IEEE.Std_logic_unsigned.all;
use IEEE.numeric_std.all;
--use IEEE.numeric_bit.all;
use work.all;

library UNISIM;
use UNISIM.vcomponents.all;


ENTITY deskew IS
   PORT (
      datain                  : IN std_logic_vector(7 DOWNTO 0);   
--      edgei                   : OUT std_logic_vector(2 DOWNTO 0);   
      rst                     : IN std_logic;   
      deskew_en               : IN std_logic;   
      clkdiv                  : IN std_logic;   
      dlyce                   : OUT std_logic;   
      dlyinc                  : OUT std_logic;   
      done                    : OUT std_logic);   
END deskew;

ARCHITECTURE deskew_arch OF deskew IS
   SIGNAL Current_State            :  std_logic_vector(4 DOWNTO 0);   
   SIGNAL Next_State               :  std_logic_vector(4 DOWNTO 0);   
   SIGNAL counter                  :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL center_store             :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL edgei_init               :  std_logic_vector(6 DOWNTO 0);   
   SIGNAL cnt_rst                  :  std_logic;   
   SIGNAL cnt_inc                  :  std_logic;   
   SIGNAL loadedgei                :  std_logic;   
   SIGNAL load_center              :  std_logic;   
   SIGNAL center                   :  std_logic_vector(7 DOWNTO 0); 
    
   --Declare state machine parameters
   -- Deskew Control State Machine
   CONSTANT  START                  :  std_logic_vector(4 DOWNTO 0) := "00000"; -- 0    
   CONSTANT  START_WAIT1            :  std_logic_vector(4 DOWNTO 0) := "00001"; -- 1   
   CONSTANT  START_WAIT2            :  std_logic_vector(4 DOWNTO 0) := "00010"; -- 2  
   CONSTANT  SEEK_EDGE              :  std_logic_vector(4 DOWNTO 0) := "00011"; -- 3   
   CONSTANT  INC1                   :  std_logic_vector(4 DOWNTO 0) := "00100"; -- 4   
   CONSTANT  INC1_WAIT1             :  std_logic_vector(4 DOWNTO 0) := "00101"; -- 5   
   CONSTANT  INC1_WAIT2             :  std_logic_vector(4 DOWNTO 0) := "00110"; -- 6   
   CONSTANT  INC1_WAIT3             :  std_logic_vector(4 DOWNTO 0) := "00111"; -- 7   
   CONSTANT  EDGE1                  :  std_logic_vector(4 DOWNTO 0) := "01000"; -- 8   
   CONSTANT  INC2                   :  std_logic_vector(4 DOWNTO 0) := "01001"; -- 9   
   CONSTANT  INC2_WAIT1             :  std_logic_vector(4 DOWNTO 0) := "01010"; -- 10   
   CONSTANT  INC2_WAIT2             :  std_logic_vector(4 DOWNTO 0) := "01011"; -- 11   
   CONSTANT  INC2_WAIT3             :  std_logic_vector(4 DOWNTO 0) := "01100"; -- 12   
   CONSTANT  EDGE2                  :  std_logic_vector(4 DOWNTO 0) := "01101"; -- 13   
   CONSTANT  EDGE2_WAIT1            :  std_logic_vector(4 DOWNTO 0) := "01110"; -- 14   
   CONSTANT  CENTER_DEC             :  std_logic_vector(4 DOWNTO 0) := "01111"; -- 15   
   CONSTANT  CHECK_CENTER           :  std_logic_vector(4 DOWNTO 0) := "10000"; -- 16   
   CONSTANT  DESKEW_DONE            :  std_logic_vector(4 DOWNTO 0) := "10001"; -- 17   
   CONSTANT  DONE_WAIT1             :  std_logic_vector(4 DOWNTO 0) := "10010"; -- 18   
   CONSTANT  DONE_WAIT2             :  std_logic_vector(4 DOWNTO 0) := "10011"; -- 19   

   SIGNAL edgei_int              :  std_logic_vector(6 DOWNTO 0);   
   SIGNAL dlyce_int              :  std_logic;   
   SIGNAL dlyinc_int             :  std_logic;   
   SIGNAL done_int               :  std_logic;   

BEGIN
   dlyce <= dlyce_int;
   dlyinc <= dlyinc_int;
   done <= done_int;
	center <= STD_LOGIC_VECTOR(UNSIGNED(center_store) SRL 1);
	edgei_int(6) <= datain(7) XOR datain(6) ;
   edgei_int(5) <= datain(6) XOR datain(5) ;
   edgei_int(4) <= datain(5) XOR datain(4) ;
   edgei_int(3) <= datain(4) XOR datain(3) ;
   edgei_int(2) <= datain(3) XOR datain(2) ;
   edgei_int(1) <= datain(2) XOR datain(1) ;
   edgei_int(0) <= datain(1) XOR datain(0) ;

   -- All-purpose counter
   PROCESS (clkdiv, rst)
   BEGIN
      IF (rst = '1') THEN
         counter <= (others=>'0');   
      ELSIF rising_edge(clkdiv) THEN
         IF (cnt_rst = '1') THEN
            counter <= (others=>'0');    
         ELSIF (cnt_inc = '1') THEN
            counter <= counter + X"01";    
         ELSE
            counter <= counter;    
         END IF;
      END IF;
   END PROCESS;

   -- Load center count
   PROCESS (clkdiv, rst)
   BEGIN
      IF (rst = '1') THEN
         center_store <= (others=>'0');    
      ELSIF rising_edge(clkdiv) THEN
         IF (load_center = '1') THEN
            center_store <= counter;    
         ELSE
            center_store <= center_store;    
         END IF;
      END IF;
   END PROCESS;

   -- Load initial edge information
   PROCESS (clkdiv, rst)
   BEGIN
      IF (rst = '1') THEN
         edgei_init <= (others=>'0');    
      ELSIF rising_edge(clkdiv) THEN
         IF (loadedgei = '1') THEN
            edgei_init <= edgei_int;    
         ELSE
            edgei_init <= edgei_init;    
         END IF;
      END IF;
   END PROCESS;

   -- Current State Logic
   PROCESS (clkdiv, rst)
   BEGIN
      IF (rst = '1') THEN
         Current_State <= START;    
      ELSIF rising_edge(clkdiv) THEN
         Current_State <= Next_State;    
      END IF;
   END PROCESS;

   -- Output forming logic
   PROCESS (Current_State)
   BEGIN
      CASE Current_State IS
         WHEN START =>
                  cnt_rst <= '1';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';   
			    
	    -- Insert wait states after START to account for pipeline stages
	    -- in channel select MUX.
         WHEN START_WAIT1 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 
			      
         WHEN START_WAIT2 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';  

	    -- Look for a pattern out of the ISERDES that contains an edge
	    -- which can be monitored for movement. 			     
         WHEN SEEK_EDGE =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '1';    
                  load_center <= '0';    
                  done_int <= '0'; 

	    -- Increment tap delay line until next left edge is found (edge pattern
	    -- shifts right by one)			      
         WHEN INC1 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '1';    
                  dlyinc_int <= '1';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0'; 
			      
         WHEN INC1_WAIT1 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';    
                  dlyinc_int <= '0';    
                  loadedgei <= '0';    
                  load_center <= '0';    
                  done_int <= '0';   
			    
         WHEN INC1_WAIT2 =>
                  cnt_rst <= '0';    
                  cnt_inc <= '0';    
                  dlyce_int <= '0';