📄 xlli_mainstone_defs.inc
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.equ xlli_DTC_26,(0x00000000) @ 26 MHz setting
.equ xlli_DTC_32,(0x00000000) @ 32 MHz setting
.equ xlli_DTC_39,(0x01000100) @ 39 MHz setting
.equ xlli_DTC_45,(0x01000100) @ 45 MHz setting
.equ xlli_DTC_52,(0x01000100) @ 52 MHz setting
.equ xlli_DTC_58,(0x01000100) @ 58 MHz setting
.equ xlli_DTC_65,(0x01000100) @ 65 MHz setting
.equ xlli_DTC_68,(0x02000200) @ 68 MHz setting
.equ xlli_DTC_71,(0x02000200) @ 71 MHz setting
.equ xlli_DTC_74,(0x02000200) @ 74 MHz setting
.equ xlli_DTC_78,(0x02000200) @ 78 MHz setting
.equ xlli_DTC_81,(0x02000200) @ 81 MHz setting
.equ xlli_DTC_84,(0x02000200) @ 84 MHz setting
.equ xlli_DTC_87,(0x02000200) @ 87 MHz setting
.equ xlli_DTC_91,(0x02000200) @ 91 MHz setting
.equ xlli_DTC_94,(0x02000200) @ 94 MHz setting
.equ xlli_DTC_97,(0x02000200) @ 97 MHz setting
.equ xlli_DTC_100,(0x03000300) @ 100 MHz setting
.equ xlli_DTC_104,(0x03000300) @ 104 MHz setting
.equ xlli_DTC_110,(0x01000100) @ 110 MHz setting - SDCLK Halved
.equ xlli_DTC_117,(0x01000100) @ 117 MHz setting - SDCLK Halved
.equ xlli_DTC_124,(0x01000100) @ 124 MHz setting - SDCLK Halved
.equ xlli_DTC_130,(0x02000200) @ 130 MHz setting - SDCLK Halved
.equ xlli_DTC_136,(0x02000200) @ 136 MHz setting - SDCLK Halved
.equ xlli_DTC_143,(0x02000200) @ 143 MHz setting - SDCLK Halved
.equ xlli_DTC_149,(0x02000200) @ 149 MHz setting - SDCLK Halved
.equ xlli_DTC_156,(0x02000200) @ 156 MHz setting - SDCLK Halved
.equ xlli_DTC_162,(0x02000200) @ 162 MHz setting - SDCLK Halved
.equ xlli_DTC_169,(0x02000200) @ 169 MHz setting - SDCLK Halved
.equ xlli_DTC_175,(0x02000200) @ 175 MHz setting - SDCLK Halved
.equ xlli_DTC_182,(0x02000200) @ 182 MHz setting - SDCLK Halved
.equ xlli_DTC_188,(0x02000200) @ 188 MHz setting - SDCLK Halved
.equ xlli_DTC_195,(0x02000200) @ 195 MHz setting - SDCLK Halved
.equ xlli_DTC_201,(0x03000300) @ 201 MHz setting - SDCLK Halved
.equ xlli_DTC_208,(0x03000300) @ 208 MHz setting - SDCLK Halved
@
@ Optimal values for DRI settings for various MemClk settings (MDREFR)
@
.equ xlli_DRI_13,(0x002) @ 13 MHz setting
.equ xlli_DRI_19,(0x003)
.equ xlli_DRI_26,(0x004) @ 26 MHz setting
.equ xlli_DRI_32,(0x006)
.equ xlli_DRI_39,(0x007) @ 39 MHz setting
.equ xlli_DRI_45,(0x009)
.equ xlli_DRI_52,(0x00A) @ 52 MHz setting
.equ xlli_DRI_58,(0x00C)
.equ xlli_DRI_65,(0x00D) @ 65 MHz setting
.equ xlli_DRI_68,(0x00E)
.equ xlli_DRI_71,(0x00F) @ 71 MHz setting
.equ xlli_DRI_74,(0x010)
.equ xlli_DRI_78,(0x010) @ 78 MHz setting
.equ xlli_DRI_81,(0x011)
.equ xlli_DRI_84,(0x012) @ 84 MHz setting
.equ xlli_DRI_87,(0x013)
.equ xlli_DRI_91,(0x013) @ 91 MHz setting
.equ xlli_DRI_94,(0x014) @ 94 MHz setting
.equ xlli_DRI_97,(0x015) @ 97 MHz setting
.equ xlli_DRI_100,(0x016) @ 100 MHz setting
.equ xlli_DRI_104,(0x016) @ 104 MHz setting
.equ xlli_DRI_110,(0x018)
.equ xlli_DRI_117,(0x019) @ 117 MHz setting
.equ xlli_DRI_124,(0x01B)
.equ xlli_DRI_130,(0x01C) @ 130 MHz setting
.equ xlli_DRI_136,(0x01E)
.equ xlli_DRI_143,(0x01F)
.equ xlli_DRI_149,(0x021)
.equ xlli_DRI_156,(0x022)
.equ xlli_DRI_162,(0x024)
.equ xlli_DRI_169,(0x025) @ 169 MHz setting
.equ xlli_DRI_175,(0x027)
.equ xlli_DRI_182,(0x028)
.equ xlli_DRI_188,(0x02A)
.equ xlli_DRI_195,(0x02B)
.equ xlli_DRI_201,(0x02D)
.equ xlli_DRI_208,(0x02E) @ 208 MHz setting
.else @ ELSE not MCP package
@ Now on a discrete MS II platform with slightly better performing SDRAM
.equ xlli_DTC_13,(0x00000000) @ 13 MHz setting
.equ xlli_DTC_19,(0x00000000) @ 19 MHz setting
.equ xlli_DTC_26,(0x00000000) @ 26 MHz setting
.equ xlli_DTC_32,(0x00000000) @ 32 MHz setting
.equ xlli_DTC_39,(0x00000000) @ 39 MHz setting
.equ xlli_DTC_45,(0x00000000) @ 45 MHz setting
.equ xlli_DTC_52,(0x00000000) @ 52 MHz setting
.equ xlli_DTC_58,(0x01000100) @ 58 MHz setting
.equ xlli_DTC_65,(0x01000100) @ 65 MHz setting
.equ xlli_DTC_68,(0x01000100) @ 68 MHz setting
.equ xlli_DTC_71,(0x01000100) @ 71 MHz setting
.equ xlli_DTC_74,(0x01000100) @ 74 MHz setting
.equ xlli_DTC_78,(0x01000100) @ 78 MHz setting
.equ xlli_DTC_81,(0x01000100) @ 81 MHz setting
.equ xlli_DTC_84,(0x01000100) @ 84 MHz setting
.equ xlli_DTC_87,(0x01000100) @ 87 MHz setting
.equ xlli_DTC_91,(0x02000200) @ 91 MHz setting
.equ xlli_DTC_94,(0x02000200) @ 94 MHz setting
.equ xlli_DTC_97,(0x02000200) @ 97 MHz setting
.equ xlli_DTC_100,(0x02000200) @ 100 MHz setting
.equ xlli_DTC_104,(0x02000200) @ 104 MHz setting
.equ xlli_DTC_110,(0x01000100) @ 110 MHz setting - SDCLK Halved
.equ xlli_DTC_117,(0x01000100) @ 117 MHz setting - SDCLK Halved
.equ xlli_DTC_124,(0x01000100) @ 124 MHz setting - SDCLK Halved
.equ xlli_DTC_130,(0x01000100) @ 130 MHz setting - SDCLK Halved
.equ xlli_DTC_136,(0x01000100) @ 136 MHz setting - SDCLK Halved
.equ xlli_DTC_143,(0x01000100) @ 143 MHz setting - SDCLK Halved
.equ xlli_DTC_149,(0x01000100) @ 149 MHz setting - SDCLK Halved
.equ xlli_DTC_156,(0x01000100) @ 156 MHz setting - SDCLK Halved
.equ xlli_DTC_162,(0x01000100) @ 162 MHz setting - SDCLK Halved
.equ xlli_DTC_169,(0x01000100) @ 169 MHz setting - SDCLK Halved
.equ xlli_DTC_175,(0x01000100) @ 175 MHz setting - SDCLK Halved
.equ xlli_DTC_182,(0x02000200) @ 182 MHz setting - SDCLK Halved - Close to edge, so bump up
.equ xlli_DTC_188,(0x02000200) @ 188 MHz setting - SDCLK Halved - Close to edge, so bump up
.equ xlli_DTC_195,(0x02000200) @ 195 MHz setting - SDCLK Halved - Close to edge, so bump up
.equ xlli_DTC_201,(0x02000200) @ 201 MHz setting - SDCLK Halved - Close to edge, so bump up
.equ xlli_DTC_208,(0x02000200) @ 208 MHz setting - SDCLK Halved - Close to edge, so bump up
@
@ Optimal values for DRI settings for various MemClk settings (MDREFR)
@
.equ xlli_DRI_13,(0x002) @ 13 MHz setting
.equ xlli_DRI_19,(0x003)
.equ xlli_DRI_26,(0x005) @ 26 MHz setting
.equ xlli_DRI_32,(0x006)
.equ xlli_DRI_39,(0x008) @ 39 MHz setting
.equ xlli_DRI_45,(0x00A)
.equ xlli_DRI_52,(0x00B) @ 52 MHz setting
.equ xlli_DRI_58,(0x00D)
.equ xlli_DRI_65,(0x00E) @ 65 MHz setting
.equ xlli_DRI_68,(0x00F)
.equ xlli_DRI_71,(0x010) @ 71 MHz setting
.equ xlli_DRI_74,(0x011)
.equ xlli_DRI_78,(0x012) @ 78 MHz setting
.equ xlli_DRI_81,(0x012)
.equ xlli_DRI_84,(0x013) @ 84 MHz setting
.equ xlli_DRI_87,(0x014)
.equ xlli_DRI_91,(0x015) @ 91 MHz setting
.equ xlli_DRI_94,(0x016) @ 94 MHz setting
.equ xlli_DRI_97,(0x016) @ 97 MHz setting
.equ xlli_DRI_100,(0x017) @ 100 MHz setting
.equ xlli_DRI_104,(0x018) @ 104 MHz setting
.equ xlli_DRI_110,(0x01A)
.equ xlli_DRI_117,(0x01B) @ 117 MHz setting
.equ xlli_DRI_124,(0x01D)
.equ xlli_DRI_130,(0x01E) @ 130 MHz setting
.equ xlli_DRI_136,(0x020)
.equ xlli_DRI_143,(0x021)
.equ xlli_DRI_149,(0x023)
.equ xlli_DRI_156,(0x025)
.equ xlli_DRI_162,(0x026)
.equ xlli_DRI_169,(0x028) @ 169 MHz setting
.equ xlli_DRI_175,(0x029)
.equ xlli_DRI_182,(0x02B)
.equ xlli_DRI_188,(0x02D)
.equ xlli_DRI_195,(0x02E)
.equ xlli_DRI_201,(0x030)
.equ xlli_DRI_208,(0x031) @ 208 MHz setting
.endif @ xlli_SDRAM_WIDTH_16_BIT
@ SDRAM Settings
.ifdef xlli_SDRAM_WIDTH_16_BIT
@ Again, using the 16-bit flag since the SDRAM in question is MCP specific and currently
@ the only 16-bit bus is planned on a MCP
.equ xlli_MDCNFG_value,(0x00002BCC) @ SDRAM Config Reg (MCP Version)
.else
.equ xlli_MDCNFG_value,(0x00000AC8) @ SDRAM Config Reg (Non-MCP Version)
.endif
.equ xlli_MDMRS_value,(0x00000000) @ SDRAM Mode Reg Set Config Reg
@
@ MEMORY PHYSICAL BASE ADDRESS(S)
@
.equ xlli_SRAM_PHYSICAL_BASE,(0X5C000000) @ Physical base address for SRAM
.equ xlli_SDRAM_PHYSICAL_BASE,(0xA0000000) @ Physical base address for SDRAM
@
@ CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone
@
.equ xlli_CCCR_value,(0x00000107) @ Bulverde (HW reset value to start)
@
@ Clock Enable Register (CKEN) setting
@
.equ xlli_CKEN_value,(0x00400200) @ Data to be set into the clock enable register
@ bit 9 enables OS timers
@ Bit 22 enables memory clock
@
@ Address where system configuration data is stored
@
.equ xlli_SCR_data,(0x5C03FFFC) @ Address in SRAM where system config data is stored
@
@ Misc constants
@
.equ xlli_MemSize_1Mb,(0x00100000)
.ifdef xlli_SDRAM_SIZE_32_MB
.equ xlli_p_PageTable,(0xA1FFC000) @ Base address for memory Page Table (MCP version)
.else
.equ xlli_p_PageTable,(0xA3FFC000) @ Base address for memory Page Table (Non-MCP version)
.endif
.equ xlli_s_PageTable,(0x00004000) @ Page Table size (4K words - 16 Kb)
.ifdef POST_BUILD
.equ xlli_v_xbBOOTROM,(0x04000000) @ (0x04000000 for POST)
.else
.equ xlli_v_xbBOOTROM,(0x00000000)
.endif@
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