deng.txt

verilogHDL跑马灯程序

module aaa(clk,rst,sel,hex);
input clk;
input rst;

output[6:0] hex;
output[3:0] sel;


reg[3:0] count1;
reg[3:0] count2;
reg[3:0] count3;
reg[3:0] count4;
reg [25:0]  count;
reg[16:0] count5; 
reg[3:0]  din; 
reg[3:0]  sel;  
reg[6:0] hex;           
always@(posedge clk)
begin
     if(!rst)
       begin
	      count<=0;
	      count1<=0; 
			count2<=0;
			count3<=0; 
			count4<=0;
	    end
     else
	     if(count<50000000) count<=count+1;  		 
        else
          begin
    	     count<=0;
	
if(count1==9) 
 begin
  count1<=0; 
    if2==(count5)  
    begin
   	 count2<=0;     	  
			  if(count3==9)     
 	          begin
                count3<=0;
	            if(count4==5)                   
		            count4<=0;
		         else
		            count4<=count4+1;
		       end	
           else	count3<=count3+1;
      end
	 else
    count2<=count2+1;	
 end
else
count1<=count1+1;	
end	 
end
always @(posedge clk) 
begin 
  if(!rst) 
    begin
      hex<=7'b0111111;
      sel[3:0]<=4'b1110;
      count5<=0;	 
    end 
  else  if(count5<50000)       
		  count5<=count5+1;
      else
        begin
    	   count5<=0;
			sel[0]<=sel[3];
			sel[3:1]<=sel[2:0];     
     
		case(sel)
		 4'b1110:din<=count1;
		
		4'b1101: din<=count2;
		 
          4'b1011: din<=count3;
	 
	    4'b0111: din<=count4;
	 
	 	
     	 endcase	 
		
        begin 
        case(din) 
        4'b0000:hex<=7'b0111111;
        4'b0001:hex<=7'b0000110;
        4'b0010:hex<=7'b1011011;
        4'b0011:hex<=7'b1001111;
        4'b0100:hex<=7'b1100110;
        4'b0101:hex<=7'b1101101;
        4'b0110:hex<=7'b1111101;
        4'b0111:hex<=7'b0000111;
        4'b1000:hex<=7'b1111111;
        4'b1001:hex<=7'b1101111;
        default:hex<=7'b0111111;
        endcase 		    
       end
		 
       end 
end
endmodule