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📄 init_dspic30f4013.s

📁 USE CAN Library in PIC30 to transmit and receive CAN Message．
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12 
	MOV #0x1000, W0
	MOV W0, I2CCON

; Feature=UART1 - UART 1 configuration
	CLR U1BRG                              ; UART1 baud rate generator

; B15=UTXISEL B11=UTXBRK B10=UTXEN B9=UTXBF B8=TRMT

; B7:6=URXISEL1:0 B5=ADDEN B4=RIDLE B3=PERR B2=FERR B1=OERR B0=URXDA
	MOV #0x8000, W0                        ; enabling UART flushes buffers
	MOV W0, U1MODE
	MOV #0x0110, W0
	MOV W0, U1STA

; B15=UARTEN B13=USIDL B10=ALTIO

; B7=WAKE B6=LPBACK B5=ABAUD B2:1=PDSEL1:0 B0=STSEL
	CLR U1MODE

; Feature=UART2 - UART 2 configuration
	CLR U2BRG                              ; UART2 baud rate generator

; B15=UTXISEL B11=UTXBRK B10=UTXEN B9=UTXBF B8=TRMT

; B7:6=URXISEL1:0 B5=ADDEN B4=RIDLE B3=PERR B2=FERR B1=OERR B0=URXDA
	MOV #0x8000, W0
	MOV W0, U2MODE
	MOV #0x0110, W0
	MOV W0, U2STA

; B15=UARTEN B13=USIDL B10=ALTIO

; B7=WAKE B6=LPBACK B5=ABAUD B2:1=PDSEL1:0 B0=STSEL
	CLR U2MODE

; Feature=CAN1 - CAN bus configuration

; Always abort pending TX before init.

	MOV C1CTRL, W0

	BSET W0, #12

	MOV W0, C1CTRL

	MOV #0x1000, W1

CAN1_TX_WAIT:		; wait for PIC to signal pending

	MOV C1CTRL, W0

	AND W1, W0, W0

	BRA NZ, CAN1_TX_WAIT

; Request CAN module go into config mode so

; we can update configuration registers.

	MOV C1CTRL, W0

	BCLR W0, #8

	BCLR W0, #9

	BCLR W0, #10

	BSET W0, #10

	MOV W0, C1CTRL

; Loop until current mode is 'config'.

	MOV #0x0080, W1

	MOV #0x00E0, W2

CAN1_CONFIG_WAIT:		; 

	MOV C1CTRL, W0

	AND W2, W0, W0

	SUB W1, W0, W0

	BRA NZ, CAN1_CONFIG_WAIT

; RXFnSID: B12:2=RXFnSID10:0 B0=EXIDEN

; RXFnEIDH: B11:0=EID17:6

; RXFnEIDL: B15:10=EID5:0
	CLR C1RXF0SID
	CLR C1RXF0EIDH
	CLR C1RXF0EIDL
	CLR C1RXF1SID
	CLR C1RXF0EIDH
	CLR C1RXF0EIDL
	CLR C1RXF2SID
	CLR C1RXF2EIDH
	CLR C1RXF2EIDL
	CLR C1RXF3SID
	CLR C1RXF3EIDH
	CLR C1RXF3EIDL
	CLR C1RXF4SID
	CLR C1RXF4EIDH
	CLR C1RXF4EIDL
	CLR C1RXF5SID
	CLR C1RXF5EIDH
	CLR C1RXF5EIDL

; RXMnSID: B12:2=RXFnSID10:0 B0=EXIDEN

; RXMnEIDH: B11:0=EID17:6

; RXMnEIDL: B15:10=EID5:0
	CLR C1RXM0SID
	CLR C1RXM0EIDH
	CLR C1RXM0EIDL
	CLR C1RXM1SID
	CLR C1RXM1EIDH
	CLR C1RXM1EIDL

; TXnSID: B15:11=TXnSID10:6 B7:2=SID5:0 B1=SRR B0=EXIDEN

; TXnEID: B15:12=EID17:14 B9:0=EID13:6

; TXnDLC: B15:10=EID5:0 B9=RTR B8:7=RB1:0 B6:3=DLC3:0

; TXnCON: B6=TXABT B5=TXLARB B4=TXERR B3=TXREQ B1:0=TXPRI1:0
	CLR C1TX2SID
	CLR C1TX2EID
	MOV #0x0180, W0
	MOV W0, C1TX2DLC
	CLR C1TX2CON
	CLR C1TX1SID
	CLR C1TX1EID
	MOV #0x0180, W0
	MOV W0, C1TX1DLC
	CLR C1TX1CON
	CLR C1TX0SID
	CLR C1TX0EID
	MOV #0x0180, W0
	MOV W0, C1TX0DLC
	CLR C1TX0CON

; RXnSID: B12:2=SID10:0 B1=SRR B0=EXIDEN

; RXnEID: B11:0=EID17:6

; RXnDLC: B15:10=EID5:0 B9=RTR B8=RB1 B4=RB0 B3:0=DLC3:0

; RXnCON: B7=RXFUL B3=RXRTRO B2=DBEN B1=JTOFF B0=FILHIT0
	CLR C1RX1SID
	CLR C1RX1EID
	MOV #0x0110, W0
	MOV W0, C1RX1DLC
	CLR C1RX1CON
	CLR C1RX0SID
	CLR C1RX0EID
	MOV #0x0110, W0
	MOV W0, C1RX0DLC
	CLR C1RX0CON

; B7:6=SJWS1:0 B5:0=BRP
	CLR C1CFG1

; B14=WAKFIL B10:8=SEG2PH

; B7=BTLMODE B6=SAM B5:3=SEG1PH B2:0=PRSEG
	CLR C1CFG2

; B15=CANCAP B13=CSIDLE B12=ABAT B11=CANCKS B10:8=REQOP2:0 B7:5=OPMODE2:0 B3:1=ICODE2:0
	MOV #0x0480, W0
	MOV W0, C1CTRL

; Flags: B15=RX0OVR B14=RX1OVR B13=TXBO B12=TXEP

; Flags: B11=RXEP B10=TXWAR B9=RXWAR B8=EWARN

; Flags IF, Enables IE: B7=IVRI B6=WAK B5=ERR B4=TX2 B3=TX1 B2=TX0 B1=RX1 B0=RX0
	CLR C1INTF                             ; clear all flags
	CLR C1INTE
	CLR C1EC                               ; clear tx and rx error registers

; request post-config operating mode for CAN module
	MOV #0x0480, W0                        ; send post config settings
	MOV W0, C1CTRL

	MOV C1CTRL, W1

	MOV #0x0700, W2

	AND W1, W2, W1

	LSR W1, #0x03, W1

	MOV #0x00E0, W2

CAN1_OPMODE_WAIT:		; 

	MOV C1CTRL, W0

	AND W2, W0, W0

	SUB W1, W0, W0

	BRA NZ, CAN1_OPMODE_WAIT

; Feature=DCI - DCI configuration
	CLR DCICON1                            ; hard clear to disable during init
	MOV RXBUF0, W0                         ; flush buffer 0
	MOV RXBUF1, W0                         ; flush buffer 1
	MOV RXBUF2, W0                         ; flush buffer 2
	MOV RXBUF3, W0                         ; flush buffer 3

; B15:0=TSE15:0
	CLR TSCON

; B15:0=RSE15:0
	CLR RSCON

; B11:8=SLOT3:0 B3=ROV B2=RFUL B1=TUNF B0=TMPTY
	CLR DCISTAT

; B11:0=BCG
	CLR DCICON3

; B11:10=BLEN1:0 B8:5=COFSG3:0 B3:0=WS
	CLR DCICON2

; B15=DCIEN B13=DCISIDL B11=DLOOP B10=CSCKD B9=CSCKE B8=COFSD

; B7=UNFM B6=CSDOM B5=DJST B1:0=COFSM1:0
	CLR DCICON1

; Feature=A2D - A2D configuration
                    ; Turn off A2D before setting registers
	CLR ADCON1

; B15:0=CSSL15:0
	CLR ADCSSL

; B15:14=CH123NB1:0 B13=CH123SB B12=CH0NB B11:8=CH0SB3:0

; B7:6=CH123NA1:0 B5=CH123SA B4=CH0NA B3:0=CH0SA3:0
	CLR ADCHS

; B15:0=PCFG15:0
	CLR ADPCFG

; B12:8=SAMC4:0 B7=ADRC B5:0=ADCS5:0
	CLR ADCON3

; B15:13=VCFG2:0 B12=OFFCAL B10=CSCNA B9:8=CHPS1:0

; B7=BUFS B5:2=SMPI B1=BUFM B0=ALTS
	CLR ADCON2

; B15=ADON B13=ADSIDL B12=ADSTBY B9:8=FORM

; B7:5=SSRC B3=SIMSAM B2=ASAM B1=SAMP B0=CONV
	CLR ADCON1

; Feature=required - Interrupt flags cleared and interrupt configuration

; interrupt priorities IP

; B14:12=T1 B10:8=OC1 B6:4=IC1 B2:0=INTO
	MOV #0x4444, W0
	MOV W0, IPC0

; B14:12=T3 B10:8=T2 B6:4=OC2 B2:0=IC2
	MOV #0x4444, W0
	MOV W0, IPC1

; B14:12=AD B10:8=U1TX B6:4=U1RX B2:0=SPI1
	MOV #0x4444, W0
	MOV W0, IPC2

; B14:12=CN B10:8= BCLB6:4=I2C B2:0=NVM
	MOV #0x4444, W0
	MOV W0, IPC3

; B14:12=OC3 B10:8=IC8 B6:4=IC7 B2:0=INT1
	MOV #0x4444, W0
	MOV W0, IPC4

; B14:12=INT2 B10:8=T5 B6:4=T4 B2:0=OC4
	MOV #0x4444, W0
	MOV W0, IPC5

; B14:12=C1 B10:8=SPI2 B6:4=U2TX B2:0=U2RX
	MOV #0x4444, W0
	MOV W0, IPC6

; B14:12=IC6 B10:8=IC5 B6:4=IC4 B2:0=IC3

; B14:12=OC8 B10:8=OC7 B6:4=OC6 B2:0=OC5

; B14:12=PWM B10:8=C2 B6:4=INT4 B2:0=INT3

; B14:12=FLTA B10:8=LVD B6:4=DCI B2:0=QEI
	MOV #0x4444, W0
	MOV W0, IPC10

; external interrupt enables

; B15=NSTDIS B10=OVATE B9=OVBTE B8=COVTE

; B4=MATHERR B3=ADDRERR B2=STKERR B1=OSCFAIL
	CLR INTCON1

; B15=ALTIVT B4:0=INTnEP4:0
	CLR INTCON2

; Feature=Timer1 - Start timers

; Timers1: B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B2=TSYNC B1=TCS
	CLR T1CON

; Feature=Timer3 - Start timers

; Timers3,5:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS
	CLR T3CON

; Feature=Timer2 - Start timers

; Timers2,4:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS
	CLR T2CON

; Feature=Timer5 - Start timers

; Timers3,5:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS
	CLR T5CON

; Feature=Timer4 - Start timers

; Timers2,4:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS
	CLR T4CON

; Feature=CPU - CPU register configuration
	CLR SR
	CLR SR
	CLR W0
	CLR W1
	CLR W2

; Feature=Interrupts - enable interrupts

; feature interrupt enables IE

; B15=CN B14=BCL B13=I2C B12=NVM B11=AD B10=U1TX B9=U1RX B8=SPI1

; B7=T3 B6=T2 B5=OC2 B4=IC2 B3=T1 B2=OC1 B1=IC1 B0=INT0
	CLR IEC0

; B15:12=IC6:3 B11=C1 B10=SPI2 B9=U2TX B8=U2RX

; B7=INT2 B6=T5 B5=T4 B4=OC4 B3=OC3 B2=IC8 B1=IC7 B0=INT1
	CLR IEC1

; B12=FLTB B11=FLTA B10=LVD B9=DCI B8=QEI

; B7=PWM B6=C2 B5=INT4 B4=INT3 B3:0=OC8:5
	CLR IEC2

	return
12

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