📄 init_dspic30f4013.s
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; Initialization Code for dsPIC30F4013, Family: controller control, Package: 44-Pin TQFP 44pins
.include "p30F4013.inc"
; Filter Controls used to Generate Code:
; POR Match Filter OFF
; Provisioned Feature Filter OFF
; Masks are Ignored and uses UnMasked Register Writes
.GLOBAL _VisualInitialization
; Feature=fuses - fuses (DCR) configuration
; B15:14=FSCKM1:0 B10:8=FOS2:0 B4:0=FPR4:0
config __FOSC, 0xC703
; B15=FWDTEN B5:4=FWPSA1:0 B3:0=FWPSB3:0
config __FWDT, 0x803F
; B15=MCLREN B7=BOREN B5:4=BORV1:0 B3:0=FPWRT3:0
config __FBORPOR, 0x87B3
.text
_VisualInitialization:
; Feature=Interrupts - Disable Interrupts during configuration
; clear int flags:
; B15=CN B14=BCL B13=I2C B12=NVM B11=AD B10=U1TX B9=U1RX B8=SPI1
; B7=T3 B6=T2 B5=OC2 B4=IC2 B3=T1 B2=OC1 B1=IC1 B0=INT0
CLR IFS0
; B15:12=IC6:3 B11=C1 B10=SPI2 B9=U2TX B8=U2RX
; B7=INT2 B6=T5 B5=T4 B4=OC4 B3=OC3 B2=IC8 B1=IC7 B0=INT1
CLR IFS1
; B12=FLTB B11=FLTA B10=LVD B9=DCI B8=QEI
; B7=PWM B6=C2 B5=INT4 B4=INT3 B3:0=OC8:5
CLR IFS2
CLR IEC0
CLR IEC1
CLR IEC2
; Feature=Reset - Reset configuration
; B15=TRAPR B14=IOPWR B13=BGST B12=LVDEN B11:8=LVDL3:0
; B7=EXTR B6=SWR B5=SWDTEN B4=WDTO B3=SLEEP B2=IDLE B1=BOR B0=POR
MOV #0x0503, W0
MOV W0, RCON
; Feature=DSP - DSP core configuration
; B11=EDT B10:8=DL2:0 B7=SATA B6=SATB B5=SATDW
; B4=ACCSAT B3=IPL3 B2=PSV B1=RND B0=IF
MOV #0x0020, W0
MOV W0, CORCON
; Feature=NVM - NVM configuration - not implemented
; Feature=Oscillator - Oscillator configuration
; method to override OSCCON write protect
; B13:12=COSC1:0 B9:8=NOSC1:0
MOV.B #0x03, W0
MOV.B #0x78, W1
MOV.B #0x9A, W2
MOV.W #OSCCON, W3
MOV.B W1, [W3+1]
MOV.B W2, [W3+1]
MOV.B W0, [W3+1]
; B7:6=POST1:0 B5=LOCK B3=CF B1=LPOSCEN B0=OSWEN
CLR.B W0
MOV.B #0x46, W1
MOV.B #0x57, W2
MOV.B W1, [W3+0]
MOV.B W2, [W3+0]
MOV.B W0, [W3+0]
; Feature=A2D - A2D configuration
; force all A2D ports to digital IO at first
MOV #0xFFFF, W0
MOV W0, ADPCFG
; Feature=IOPortB - IO Ports configuration
; B15:0=B15:0
CLR PORTB ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISB
; Feature=IOPortC - IO Ports configuration
; B15:0=C15:0
CLR PORTC ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISC
; Feature=IOPortD - IO Ports configuration
; B15:0=D15:0
CLR PORTD ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISD
; Feature=IOPortF - IO Ports configuration
; B15:0=F15:0
CLR PORTF ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISF
; Feature=CN1 - Input Change Notification configuration
; B15:0=CN15:0
CLR CNEN1 ; enable change notification
CLR CNPU1 ; enable pullup change notification
; B15:0=CN21:16 B7:0=CN7:0
CLR CNEN2 ; enable change notification
CLR CNPU2 ; enable pullup change notification
; Feature=Timer1 - Timers configuration
CLR T1CON ; stop timer
; Feature=Timer2 - Timers configuration
CLR T2CON ; stop timer
; Feature=Timer3 - Timers configuration
CLR T3CON ; stop timer
; Feature=Timer4 - Timers configuration
CLR T4CON ; stop timer
; Feature=Timer5 - Timers configuration
CLR T5CON ; stop timer
; Feature=Timer1 - Timers configuration
CLR TMR1 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR1
; Feature=Timer3 - Timers configuration
CLR TMR3 ; timer register
CLR TMR3HLD ; timer holding register for 32bit
MOV #0xFFFF, W0 ; period register
MOV W0, PR3
; Feature=Timer2 - Timers configuration
CLR TMR2 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR2
; Feature=Timer5 - Timers configuration
CLR TMR4 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR4
; Feature=Timer4 - Timers configuration
CLR TMR5 ; timer register
CLR TMR5HLD ; timer holding register for 32bit
MOV #0xFFFF, W0 ; period register
MOV W0, PR5
; Feature=IC1 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC1CON
; Feature=IC2 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC2CON
; Feature=IC3 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
; Feature=IC4 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
; Feature=IC5 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
; Feature=IC6 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
; Feature=IC7 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC7CON
; Feature=IC8 - Input Capture configuration
CLR IC8CON
; Feature=OC1 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC1CON
; Feature=OC2 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC2CON
; Feature=OC3 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC3CON
; Feature=OC4 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC4CON
; Feature=OC5 - Turn off OC1 thru OC8
; associated timers need to be turned off first
; Feature=OC6 - Turn off OC1 thru OC8
; associated timers need to be turned off first
; Feature=OC7 - Turn off OC1 thru OC8
; associated timers need to be turned off first
; Feature=OC8 - Turn off OC1 thru OC8
; associated timers need to be turned off first
; Feature=OC1 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC1RS
CLR OC1R
CLR OC1CON
; Feature=OC2 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC2RS
CLR OC2R
CLR OC2CON
; Feature=OC3 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC3RS
CLR OC3R
CLR OC3CON
; Feature=OC4 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC4RS
CLR OC4R
CLR OC4CON
; Feature=OC5 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
; Feature=OC6 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
; Feature=OC7 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
; Feature=OC8 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
; Feature=SPI1 - SPI configuration
; SPInBUF: SPI n buffer
; SPInSTAT: B15=SPIEN B13=SPISIDL B6=SPITBF B5=SPIROV B0=SPIRBF
; SPInCON(H): B14=FRMEN B13=SPIFSD B11=DISSDO B10=MODE16 B9=SMP B8=CKE
; SPInCON(L): B7=SSEN B6=CKP B5=MSTEN B4:2=SPRE2:0 B1:0=PPRE1:0
MOV SPI1BUF, W0
CLR SPI1STAT
CLR SPI1CON
; Feature=I2C - I2C configuration
; B7:0: receive register bits7:0
MOV I2CRCV, W0
; B9:0: address register bits9:0
CLR I2CADD
; B8:0: baud rate generator bits 8:0
CLR I2CBRG
; B15=ACKSTAT B14=TRSTAT B10=BCL B9=GCSTAT B8=ADD10
; B7=IWCOL B6=I2COV B5=D_A B4=P B3=S B2=R_W B1=RBF B0=TBF
CLR I2CSTAT
; B15=I2CEN B13=I2CSIDL B12=SCLREL B11=IPMIEN B10=A10M B9=DISSLW B8=SMEN
; B7=GCEN B6=STREN B5=ACKDT B4=ACKEN B3=RCEN B2=PEN B1=RSEN B0=SEN
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