📄 debug.asm
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; *****************************************************************************
;* The software supplied herewith by Microchip Technology Incorporated
;* (the "Company") is intended and supplied to you, the Company's
;* customer, for use solely and exclusively with products manufactured
;* by the Company.
;*
;* The software is owned by the Company and/or its supplier, and is
;* protected under applicable copyright laws. All rights are reserved.
;* Any use in violation of the foregoing restrictions may subject the
;* user to criminal sanctions under applicable laws, as well as to
;* civil liability for the breach of the terms and conditions of this
;* license.
;*
;* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
;* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
;* TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
;* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
;* IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
;* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
;
;
; Bootloader Extension for PIC18F by Ross Fosler
; 06/06/2002 ... First full implementation
;
;
;
;
; Incomming data format:
;
; <STX><STX><DATA><CHKSUM><ETX>
; / \
; ________/ \____________________________
; / \
; <COMMAND><DLEN><ADDRL><ADDRH><ADDRU><DATA>...
;
; Definitions:
;
; STX - Start of packet indicator
; ETX - End of packet indicator
; LEN - Length of incomming packet
; DATA - General data up to 255 bytes
; CHKSUM - The 8-bit two's compliment sum of LEN & DATA
; COMMAND - Base command
; DLEN - Length of data associated to the command
; ADDR - Address up to 24 bits
; DATA - Data (if any)
;
;
; Commands:
;
; RD_VER 0x00 Read Version Information
; RD_MEM 0x01 Read Program Memory
; WR_MEM 0x02 Write Program Memory
; ER_MEM 0x03 Erase Program Memory
; RD_EE 0x04 Read EEDATA Memory
; WR_EE 0x05 Write EEDATA Memory
; RD_CONFIG 0x06 Read Config Memory
; WT_CONFIG 0x07 Write Config Memory
;
; *****************************************************************************
; *****************************************************************************
; #include P18F452.INC ; Standard include
; #include P18F8720.inc
#include bootload.inc
; *****************************************************************************
; *****************************************************************************
#define MINOR_VERSION 0x00 ; Version
#define MAJOR_VERSION 0x01
#define RC_DLE 0x01
#define RC_STX 0x02
#define STX 0x0F
#define ETX 0x04
#define DLE 0x05
#define BIT_RATE d'10'
;#define TBLWT_BUG ; Timing bug found in some PIC18Fxx20s
; *****************************************************************************
; *****************************************************************************
_BOOTVAR UDATA_ACS
CHKSUM res 1 ; Checksum accumulator
COUNTER res 1 ; General counter
ABTIME_H res 1
ABTIME_L res 1
RXDATA res 1
TXDATA res 1
C_INTCON res 1
; Frame Format
;
; <STX><STX>[<COMMAND><DATALEN><ADDRL><ADDRH><ADDRU><...DATA...>]<CHKSUM><ETX>
DATA_BUFF ; Start of receive buffer
COMMAND res 1 ; Data mapped in receive buffer
DATA_COUNT res 1
ADDRESS_L res 1
ADDRESS_H res 1
ADDRESS_U res 1
PACKET_DATA res 1
; *****************************************************************************
; *****************************************************************************
pmwtpi macro ; tblwt*+ macro for PIC18Fxx20 bug
IFDEF TBLWT_BUG
tblwt *
tblrd *+
ELSE
tblwt *+
ENDIF
endm
; *****************************************************************************
; *****************************************************************************
_STARTUP CODE 0x00
; *****************************************************************************
bra Setup
; *****************************************************************************
_INT_VECT_H CODE 0x08
; *****************************************************************************
bra IntVectH
; *****************************************************************************
_INT_VECT_L CODE 0x18
; *****************************************************************************
bra IntVectL
; *****************************************************************************
_DEBUG_CODE CODE
; *****************************************************************************
; Setup the appropriate registers.
Setup
bcf TRISC, 6 ; Setup tx pin
; bsf TRISC, 7 ; Setup rx pin
movlw b'10010000' ; Setup rx and tx
movwf RCSTA1
movlw b'00100110'
movwf TXSTA1
movlw BIT_RATE
movwf SPBRG1
; *****************************************************************************
; *****************************************************************************
; Read and parse the data.
StartOfLine
rcall RdRS232 ; Get second <STX>
xorlw STX
bnz StartOfLine ; Otherwise go back for another character
StartOfLineAgain
lfsr 0, DATA_BUFF ; Point to the buffer
clrf CHKSUM ; Reset checksum
clrf COUNTER ; Reset buffer count
GetNextDat
rcall RdRS232 ; Get the data
xorlw STX ; Check for a STX
bz StartOfLineAgain ; Yes, start over
NoSTX
movf RXDATA, W
xorlw ETX ; Check for a ETX
bz CheckSum ; Yes, examine checksum
NoETX
movf RXDATA, W
xorlw DLE ; Check for a DLE
bnz NoDLE
rcall RdRS232 ; Yes, Get the next byte
NoDLE
movf RXDATA, W
addwf CHKSUM, F ; Get sum
movwf POSTINC0 ; Store the data
dcfsnz COUNTER, F ; Limit buffer to 256 bytes
bra StartOfLine
bra GetNextDat
CheckSum
movf CHKSUM ; Checksum test
bnz StartOfLine
; ***********************************************
; ***********************************************
; Pre-setup, common to all commands.
movf ADDRESS_L, W ; Set all possible pointers
movwf TBLPTRL
movwf EEADR
movwf FSR2L
movf ADDRESS_H, W
movwf TBLPTRH
movwf EEADRH
movwf FSR2H
movff ADDRESS_U, TBLPTRU
lfsr FSR0, PACKET_DATA
movf DATA_COUNT, W ; Setup counter
movwf COUNTER
btfsc STATUS, Z
reset ; Non valid count (Special Command)
; ***********************************************
; ***********************************************
; Test the command field and sub-command.
CheckCommand
movf COMMAND, W ; Test for a valid command
sublw d'10'
bnc StartOfLine
movlw high (CheckCommand)
movwf PCLATH ; Setup for a calculated jump
clrf PCLATU
rlncf COMMAND, W ; Jump
addwf PCL, F
bra ReadVersion
bra ReadProgMem
bra WriteProgMem
bra EraseProgMem
bra ReadEE
bra WriteEE
bra ReadProgMem ;ReadConfig
bra WriteConfig
bra ReadSRAM
bra WriteSRAM
bra VectorToAddr
; ***********************************************
; ***********************************************
; Commands
;
; In: <STX><STX>[<0x00><0x02>]<0xFF><ETX>
; OUT: <STX><STX>[<0x00><VERL><VERH>]<CHKSUM><ETX>
ReadVersion
movlw MINOR_VERSION
movwf DATA_BUFF + 2
movlw MAJOR_VERSION
movwf DATA_BUFF + 3
movlw 0x04
bra WritePacket
; In: <STX><STX>[<0x01><DLEN><ADDRL><ADDRH><ADDRU>]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x01><DLEN><ADDRL><ADDRH><ADDRU><DATA>...]<CHKSUM><ETX>
ReadProgMem
tblrd *+ ; Fill buffer
movff TABLAT, POSTINC0
decfsz COUNTER, F
bra ReadProgMem ; Not finished then repeat
movf DATA_COUNT, W ; Setup packet length
addlw 0x05
bra WritePacket
; In: <STX><STX>[<0x02><DLENBLOCK><ADDRL><ADDRH><ADDRU><DATA>...]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x02>]<CHKSUM><ETX>
WriteProgMem
movlw b'11111000' ; Force a boundry
andwf TBLPTRL, F
movlw 0x08
Lp1 movff POSTINC0, TABLAT ; Load the holding registers
pmwtpi ; Same as tblwt *+
decfsz WREG, F
bra Lp1
tblrd *- ; Point back into the block
movlw b'10000100' ; Setup writes
movwf EECON1
rcall StartWrite ; Write the data
tblrd *+ ; Point to the beginning of the next block
decfsz COUNTER, F
bra WriteProgMem ; Not finished then repeat
bra SendAcknowledge ; Send acknowledge
; In: <STX><STX>[<0x03><DLENROW><ADDRL><ADDRH><ADDRL>]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x03>]<CHKSUM><ETX>
EraseProgMem
movlw b'10010100' ; Setup writes
movwf EECON1
rcall StartWrite ; Erase the row
movlw 0x40 ; Point to next row
addwf TBLPTRL, F
clrf WREG
addwfc TBLPTRH, F
addwfc TBLPTRU, F
decfsz COUNTER, F
bra EraseProgMem
bra SendAcknowledge ; Send acknowledge
; In: <STX><STX>[<0x04><DLEN><ADDRL><ADDRH><0x00>]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x04><DLEN><ADDRL><ADDRH><0x00><DATA>...]<CHKSUM><ETX>
ReadEE
clrf EECON1
bsf EECON1, RD ; Read the data
movff EEDATA, POSTINC0
infsnz EEADR, F ; Adjust EEDATA pointer
incf EEADRH, F
decfsz COUNTER, F
bra ReadEE ; Not finished then repeat
movf DATA_COUNT, W ; Setup packet length
addlw 0x05
bra WritePacket
; In: <STX><STX>[<0x05><DLEN><ADDRL><ADDRH><0x00><DATA>...]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x05>]<CHKSUM><ETX>
WriteEE
movff POSTINC0, EEDATA
movlw b'00000100' ; Setup for EEData
movwf EECON1
rcall StartWrite
btfsc EECON1, WR ; Write and wait
bra $ - 2
infsnz EEADR, F ; Adjust EEDATA pointer
incf EEADRH, F
decfsz COUNTER, F
bra WriteEE ; Not finished then repeat
bra SendAcknowledge ; Send acknowledge
; In: <STX><STX>[<0x06><DLEN><ADDRL><ADDRH><ADDRU>]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x06><DLEN><ADDRL><ADDRH><ADDRU><DATA>...]<CHKSUM><ETX>
;ReadConfig
; In: <STX><STX>[<0x07><DLEN><ADDRL><ADDRH><ADDRU><DATA>...]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x07>]<CHKSUM><ETX>
WriteConfig
movlw b'11000100'
movwf EECON1
movff POSTINC0, TABLAT ; Write to config area
tblwt *
rcall StartWrite
tblrd *+
decfsz COUNTER, F
bra WriteConfig ; Not finished then repeat
bra SendAcknowledge ; Send acknowledge
; In: <STX><STX>[<0x08><DLEN><ADDRL><ADDRH>]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x08><DLEN><ADDRL><ADDRH><DATA>...]<CHKSUM><ETX>
ReadSRAM
movff POSTINC2, POSTINC0 ; Read the data
decfsz COUNTER, F
bra ReadSRAM ; Not finished then repeat
movf DATA_COUNT, W ; Setup packet length
addlw 0x05
bra WritePacket
; In: <STX><STX>[<0x09><DLEN><ADDRL><ADDRH><DATA>...]<CHKSUM><ETX>
; OUT: <STX><STX>[<0x09>]<CHKSUM><ETX>
WriteSRAM
movff POSTINC0, POSTINC2
decfsz COUNTER, F
bra WriteSRAM ; Not finished then repeat
bra SendAcknowledge ; Send acknowledge
; In: <STX><STX>[<0x0A><DLEN><ADDRL><ADDRH><ADDRU>]<CHKSUM><ETX>
VectorToAddr
incf STKPTR, F ; Load the return address
movlw UPPER ExecSubRoutine
movwf TOSU
movlw HIGH ExecSubRoutine
movwf TOSH
movlw LOW ExecSubRoutine
movwf TOSL
movff ADDRESS_U, PCLATU ; Vector
movff ADDRESS_H, PCLATH
movf ADDRESS_L, W
movwf PCL
ExecSubRoutine
movff INTCON, C_INTCON
clrf INTCON
bra SendAcknowledge ; Send acknowledge
; ***********************************************
; ***********************************************
; Send the data buffer back.
;
; <STX><STX>[<DATA>...]<CHKSUM><ETX>
SendAcknowledge
movlw 0x01 ; Send acknowledge
WritePacket
movwf COUNTER
movlw STX ; Send start condition
rcall WrRS232
rcall WrRS232
clrf CHKSUM ; Reset checksum
lfsr FSR0, DATA_BUFF ; Setup pointer to buffer area
SendNext ; Send DATA
movf POSTINC0, W
addwf CHKSUM
rcall WrData
decfsz COUNTER, F
bra SendNext
negf CHKSUM ; Send checksum
movf CHKSUM, W
rcall WrData
movlw ETX ; Send stop condition
rcall WrRS232
bra StartOfLine
; *****************************************************************************
; *****************************************************************************
; Write a byte to the serial port.
WrData
movwf TXDATA ; Save the data
xorlw STX ; Check for a STX
bz WrDLE ; No, continue WrNext
movf TXDATA, W
xorlw ETX ; Check for a ETX
bz WrDLE ; No, continue WrNext
movf TXDATA, W
xorlw DLE ; Check for a DLE
bnz WrNext ; No, continue WrNext
WrDLE
movlw DLE ; Yes, send DLE first
rcall WrRS232
WrNext
movf TXDATA, W ; Then send STX
WrRS232
clrwdt
btfss PIR1, TXIF ; Write only if TXREG is ready
bra $ - 2
movwf TXREG1 ; Start sending
return
; *****************************************************************************
; *****************************************************************************
RdRS232
clrwdt
btfsc RCSTA1, OERR ; Reset on overun
reset
btfss PIR1, RCIF ; Wait for data from RS232
bra $ - 2
movf RCREG1, W ; Save the data
movwf RXDATA
return
; *****************************************************************************
; *****************************************************************************
; Unlock and start the write or erase sequence.
StartWrite
clrwdt
movlw 0x55 ; Unlock
movwf EECON2
movlw 0xAA
movwf EECON2
bsf EECON1, WR ; Start the write
nop
return
; *****************************************************************************
; *****************************************************************************
WaitForRise
btfsc PORTC, 7 ; Wait for a falling edge
bra WaitForRise
clrwdt
WtSR
btfss PORTC, 7 ; Wait for starting edge
bra WtSR
return
; *****************************************************************************
; *****************************************************************************
_REMAP_INT_VECT_H CODE 0x208
; *****************************************************************************
IntVectH
; *****************************************************************************
_REMAP_INT_VECT_L CODE 0x218
; *****************************************************************************
IntVectL
END
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