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📄 cc2500.asm.bak

📁 cc2500的跳频发送程式,有需要的朋友可以参考一下哟
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;***************************************************************************
;F: File Name: 	cc2500.asm.
;F: Build Date:	2006/11/3.
;F: Programer:	stone_zen.
;F:
;***************************************************************************





;*****************************************************************
;F: Function Name: F_InitalCC2500.
;F:
;F: Describe:
;F:  configuration the cc2500 registers.
;F:
;*****************************************************************
F_InitalCC2500:
	lds	R_PortA,0;
	opa	R_PortA;
	
	lds	R_Delay,4;
	call	F_DelxxUS;
	ori*	R_PortA,D_CSn;
	opa	R_PortA;
	
	lds	R_Delay,10;
	call	F_DelxxUS;
	lds	R_ParLow,CMD_CC2500_SRES%16;
	lds	R_ParHigh,CMD_CC2500_SRES/16;
	call	F_CC2500WRStrobe;
	
	lds	R_Delay,4;
	call	F_DelxxUS;
	andi*	R_PortA,D_NCSn;        
	opa	R_PortA;
L_WaitSOLo01:
	ipb	R_WrkReg1;
	jb3	L_WaitSOLo01;   只有再次检到低时才算RESET 完成。
;================================================
;================================================		
;开始初始化配置寄存器的内容。
	call	F_WRCC2500Bit;
	lds	R_ParHigh,40h/16
	lds	R_ParLow,40h%16;  设为BURST write Mode.
	call	F_WRCC2500_REG_Addr;
;======================================
;Addr 0x00 IOCFG2.
	lds	R_ParLow,47H%16;         当同步字被送出时GDO2 pin产生一个低信号.
	lds	R_ParHigh,47H/16;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x01 IOCFG1.
	lds	R_ParLow,2eh%16;         此脚功能不用。
	lds	R_ParHigh,2eh/16;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x02 IOCFG0.
	lds	R_ParLow,46h%16;
	lds	R_ParHigh,46h/16;
	call	F_WRCC2500_ABYTE;     此脚功能不用。
;======================================
;Addr 0x03 FIFOTHR.
	lds	R_ParLow,7; 	      TX FIFO 超过33个字节产生溢出。	
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x04 SYNC1.
	lds	R_ParLow,03h;
	lds	R_ParHigh,0dh;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x05 SYNC0.
	lds	R_ParLow,01h;        同步字为0xd391.
	lds	R_ParHigh,09h;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x06 PKTLEN.       
	lds	R_ParLow,4;          每个包的长度为2BYTE。
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x07 PKTCTRL1.
	lds	R_ParLow,5;
	lds	R_ParHigh,0;         在TX 模式下，保留上电初始设置。
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x08 PKTCTRL0.
	lds	R_ParLow,04h;        固定包，允许CRC功能。
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x09 ADDR.
	;ipd	R_ParLow;            0~15 address.
	lds	R_ParLow,4;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x0A CHANNR.
	ipd	R_ParLow;	     0~15 AS CHANNER VALUE。	
	;lds	R_ParLow,2;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x0B FSCTRL1.
	lds	R_ParLow,0dh;        IF frequency of 254kHz,
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x0C FSCTRL0.
	lds	R_ParLow,0;          Resolution is FXTAL/214 (1.5kHz-1.7kHz); range is ±186kHz to
				    ;±217kHz, dependent of XTAL frequency.
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x0D FREQ2.
	lds	R_ParLow,0ch;       2464MHz-2483.4MHz (0-97)
	lds	R_ParHigh,05h;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x0E FREQ1.
	lds	R_ParLow,01h;
	lds	R_ParHigh,0bh;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x0F FREQ0.
	lds	R_ParLow,0bh;
	lds	R_ParHigh,03h;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x10 MDMCFG4.
	lds	R_ParLow,0dh;
	lds	R_ParHigh,02h;
	call	F_WRCC2500_ABYTE; 203kHz channel filter bandwidth,
;======================================
;Addr 0x11 MDMCFG3.
	lds	R_ParLow,0bh;
	lds	R_ParHigh,03h;
	call	F_WRCC2500_ABYTE; data rate of 115.051kbps.
;======================================
;Addr 0x12 MDMCFG2.
	lds	R_ParLow,02h;
	lds	R_ParHigh,07h;
	call	F_WRCC2500_ABYTE; 2-FSK/disable Manchester encoding/decoding/16/16 sync word bits detected.
;======================================
;Addr 0x13 MDMCFG1.
	lds	R_ParLow,03h;
	lds	R_ParHigh,02h;
	call	F_WRCC2500_ABYTE; disable Forward Error Correction (FEC)/
;======================================
;Addr 0x14 MDMCFG0.
	lds	R_ParLow,0fh;
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE; give 199.951kHz channel spacing.  
;======================================
;Addr 0x15 DEVIATN.
	lds	R_ParLow,01h;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;  give ±47.607kHz deviation,
;======================================
;Addr 0x16 MCSM2.
	lds	R_ParLow,07h;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x17 MCSM1.
	lds	R_ParLow,0;
	lds	R_ParHigh,3;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x18 MCSM0.
	lds	R_ParLow,8;      When going from IDLE to RX or TX (or FSTXON)
	lds	R_ParHigh,1;     Approx. 146μs – 171μs
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x19 FOCCFG. 
	lds	R_ParLow,0eh;      Frequency offset compensation configuration.
	lds	R_ParHigh,1;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x1A BSCFG.
	lds	R_ParLow,0ch;    Bit Synchronization configuration.
	lds	R_ParHigh,6;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x1B AGCTRL2.
	lds	R_ParLow,3;      AGC control register.
	lds	R_ParHigh,0ch;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x1C AGCTRL1.
	lds	R_ParLow,0;      AGC control register.
	lds	R_ParHigh,4;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x1D AGCTRL0.
	lds	R_ParLow,1;      AGC control register.
	lds	R_ParHigh,9;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x1E WOREVT1.
	lds	R_ParLow,7;      High byte of Event 0 timeout register.
	lds	R_ParHigh,8;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x1F WOREVT0.
	lds	R_ParLow,0bh;     Low byte of Event 0 timeout register.
	lds	R_ParHigh,6;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x20 WORCTRL.
	lds	R_ParLow,0bh;    
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x21 FREND1.
	lds	R_ParLow,06h;   Front end RX configuration.
	lds	R_ParHigh,0bh;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x22 FREND0.
	lds	R_ParLow,0;
	lds	R_ParHigh,1;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x23 FSCAL3.
	lds	R_ParLow,0ah;     Frequency synthesizer calibration configuration and result register.
	lds	R_ParHigh,0eh;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x24 FSCAL2.
	lds	R_ParLow,0ah;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x25 FSCAL1.
	lds	R_ParLow,0;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x26 FSCAL0.
	lds	R_ParLow,1;
	lds	R_ParHigh,1;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x27 RCCTRL1.
	lds	R_ParLow,01h;
	lds	R_ParHigh,04h;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x28 RCCTRL0.
	lds	R_ParLow,0;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x29 FSTEST.
	lds	R_ParLow,9;
	lds	R_ParHigh,5;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x2A PTEST.
	lds	R_ParLow,0fh;
	lds	R_ParHigh,07h;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x2B AGCTEST.
	lds	R_ParLow,0fh;
	lds	R_ParHigh,03h;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x2C TEST2.
	lds	R_ParLow,0fh;
	lds	R_ParHigh,8;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x2D TEST1.
	lds	R_ParLow,1;
	lds	R_ParHigh,2;
	call	F_WRCC2500_ABYTE;
;======================================
;Addr 0x2E TETS0.
	lds	R_ParLow,0bh;
	lds	R_ParHigh,0;
	call	F_WRCC2500_ABYTE;
	
	ori*	R_PortA,D_CSn;       CSn pin ouput high pulse.
	opa	R_PortA;
	
	lds	R_Delay,2;
	call	F_DelxxUS;
	andi*	R_PortA,D_NCSn;        
	opa	R_PortA;
L_WaitSOLow03:
	ipb	R_WrkReg1;          waiting for the SO pin of cc2500 get low.
	jb3	L_WaitSOLow03;	
	
	call	F_WRCC2500Bit;     设置发射功率。
	lds	R_ParLow,0eh;
	lds	R_ParHigh,07h;
	call	F_WRCC2500_REG_Addr;  地址3EH为功率控制寄存器。 
	
	lds	R_ParLow,0fh;      PATABLE byte0.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE

	lds	R_ParLow,0fh;      PATABLE byte1.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	lds	R_ParLow,0fh;      PATABLE byte2.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	lds	R_ParLow,0fh;      PATABLE byte3.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	lds	R_ParLow,0fh;      PATABLE byte4.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	lds	R_ParLow,0fh;      PATABLE byte5.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	lds	R_ParLow,0fh;      PATABLE byte6.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	lds	R_ParLow,0fh;      PATABLE byte7.
	lds	R_ParHigh,0fh;
	call	F_WRCC2500_ABYTE
	
	ori*	R_PortA,D_CSn;       CSn pin ouput low->high pulse.
	opa	R_PortA;
	
	
	lds	R_ParLow,CMD_CC2500_SFTX%16;
	lds	R_ParHigh,CMD_CC2500_SFTX/16;
	call	F_CC2500WRStrobe;
	
	lds	R_ParLow,CMD_CC2500_SFRX%16;
	lds	R_ParHigh,CMD_CC2500_SFRX/16;
	call	F_CC2500WRStrobe;
	
	
	lds	R_ParLow,CMD_CC2500_SCAL%16;
	lds	R_ParHigh,CMD_CC2500_SCAL/16;
	call	F_CC2500WRStrobe;
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