recordertx.lst

cc2500的跳频发送程式,有需要的朋友可以参考一下哟

00001              ;*********************************************************************
00002              ;P: Project Name:	recorderTX.
00003              ;P: Body:		TM8706+CC2500.
00004              ;P: Build Date:		2006/11/2.
00005              ;P: Version:		v1.0
00006              ;*********************************************************************
00007              .CHIP TM8706
00008              .data
00009              	org	000h;
00010              R_AddrCode	dn	1;
00011              R_KeyWakeDel	dn	1;
   12 0031        D_KeyWakeDel	equ	6; 15.625ms x 6 =93.7ms.
0013   
00014              R_TempAcc	dn	1;
00015              R_TempStatus	dn	1;
0016   
00017              R_TimerSendLo	dn	2;
   18 0005        R_TimerSendHi	equ	R_TimerSendLo+1;
0019   
   20 0037        D_TimerSendLo	equ	10;
   21 0038        D_TimerSendHi	equ	0;
0022   
00023              R_SendCommandLo	dn	2;
   24 003B        R_SendCommandHi	equ	R_SendCommandLo+1;
   25 003C        D_ScanCommand	equ	0ffh;
   26 003D        D_K1Command	equ	01h;
   27 003F        D_K2Commnad	equ	02h;
   28 0004        D_K3Command	equ	04h;
   29 0008        D_K4Command	equ	08h;
0030   
0031   
00032              R_Delay		dn	1;
00033              R_cc2500WRBuf	dn	1;
00034              R_cc2500Count	dn	1;
0035   
00036              R_ParLow	dn	2;
   37 00F5        R_ParHigh	equ	R_ParLow+1;
0038   
00039              R_LoopSend	dn	1;
0040   
00041              R_RdAddrLow	dn	2;
   42 00FA        R_RdAddrHigh	equ	R_RdAddrLow+1;
0043   
00044              R_TempWrk	dn	1;
0045   
00046              	org	070h;
00047              R_IntWrk	dn	1;Only use in interrupt for temp variay.
0048   
0049   
00050              R_WrkReg1	dn	1;
00051              R_WrkReg2	dn	2;
00052              R_WrkReg3	dn	3;
0053   
0054   
00055              R_Flags1	dn	1;
   56 0007        B_NormalStop	equ	0001b; 0: normal mode; 1: STOP Mode.
   57 0008        B_KeySend	equ	0010b;
0058   
00059              R_KeyStep	dn	1;
   60 000B        D_ChkStep	equ	0;
   61 000C        D_DelStep	equ	1;
   62 000D        D_WaitStep	equ	2;
   63 000E        D_RelaseStep	equ	3;
0064   
00065              R_KeyVal	dn	1;
   66 0011        D_K1Key		equ	1;
   67 0012        D_K2Key		equ	2;
   68 0013        D_K3Key		equ	4;
   69 0014        D_K4Key		equ	8;
0070   
00071              R_PortA		dn	1;
0072   
00073              ;==================================================
00074              ;==================================================
00075              ;Define the constrant.
   76 001B        D_CSn		equ	0100b; PortA Bit3.
   77 001C        D_NCSn		equ	1011b;
   78 001D        D_SCLK		equ	0010b; PortA Bit2.
   79 001E        D_NSCLK		equ	1101b;
   80 001F        D_SI		equ	0001b; PortA Bit1. cc2500 input port.
   81 0020        D_NSI		equ	1110b;
0082   
   83 0022        D_SO		equ	1000b; PortB bIT4. cc2500 output port.
   84 0023        D_NSO		equ	0111b;
   85 0024        D_LowBat	equ	0100b; PortB bit3.
   86 0025        D_NLowBat	equ	1011b;
   87 0026        D_GDO2		equ	0010b; PortB bit2. cc2500 GDO2 Port.
   88 0027        D_NGDO2		equ	1101b;
   89 0028        D_GDO1		equ	0001b; PortB Bit1. cc2500 GDO1 Port.
   90 0029        D_NGDO1		equ	1110b;
0091   
   92 002B        D_PreIntEnable	equ	00001000b; Enable the pre-divider interrupt.
   93 002C        D_Tmr1IntEnable	equ	00000010b; Enable the timer1 interrupt.
0094   
0095   
   96 0001        D_RFLED		equ	0001b;
   97 0001        D_LowBatLED	equ	0001b;
   98 0001        R_RFLEDBuf	equ	1;
   99 0000        R_LowBatLEDBuf	equ	2;
0100   
0101   	.INCLUDE	cc2500.inc (D:\MyWorks\RFPj\code\TX\CC2500.INC)
00001+              ;****************************************************************************
00002+              ;F: File Name:	cc2500.inc.
00003+              ;F: Build Date:	2006/11/3.
00004+              ;F:
00005+              ;F:
00006+              ;****************************************************************************
0007+  
00008+              ;=======================================================
00009+              ;=======================================================
00010+              ;Define the Command Strobes Register.
   11 0030        CMD_CC2500_SRES		equ		30h; reset chip.
   12 0031        CMD_CC2500_SFSTXON	equ		31h; Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
00013+              					   ; Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
   14 0032        CMD_CC2500_SXOFF	equ		32h; Turn off crystal oscillator.
   15 0033        CMD_CC2500_SCAL		equ		33h; Calibrate frequency synthesizer and turn it off (enables quick start).
   16 0034        CMD_CC2500_SRX		equ		34h; Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.
   17 0035        CMD_CC2500_STX		equ		35h; In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
00018+              					   ; If in RX state and CCA is enabled: Only go to TX if channel is clear.
   19 0036        CMD_CC2500_SIDLE	equ		36h; Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
   20 0037        CMD_CC2500_SAFC		equ		37h; Perform AFC adjustment of the frequency synthesizer as outlined in section 23.1.
   21 0038        CMD_CC2500_SWOR		equ		38h; Start automatic RX polling sequence (Wake-on-Radio) as described in section 28.5.
   22 0039        CMD_CC2500_SPWD		equ		39h; Enter power down mode when CSn goes high.
   23 003A        CMD_CC2500_SFRX		equ		3ah; Flush the RX FIFO buffer.
   24 003B        CMD_CC2500_SFTX		equ		3bh; Flush the TX FIFO buffer.
   25 003C        CMD_CC2500_SWORRST	equ		3ch; Reset real time clock.
   26 003D        CMD_CC2500_SNOP		equ		3dh; No operation. May be used to pad strobe commands to two bytes for simpler software.
   27 003F        DMD_CC2500_FIFO		equ		3fh;
0028+  
00029+              ;=========================================================
00030+              ;=========================================================
00031+              ;Define the status register.
   32 00F0        STS_CC2500_PARTNUM	equ		0f0h;Part number for CC2500.
   33 00F1        STS_CC2500_VERSION	equ		0f1h;Current version number.
   34 00F2        STS_CC2500_FREQEST	equ		0f2h;Frequency Offset Estimate.
   35 00F3        STS_CC2500_LQI		equ		0f3h;Demodulator estimate for Link Quality.
   36 00F4        STS_CC2500_RSSI		equ		0f4h;Received signal strength indication.
   37 00F5        STS_CC2500_MARCSTATE	equ		0f5h;Control state machine state.
   38 00F6        STS_CC2500_WORTIME1	equ		0f6h;High byte of WOR timer.
   39 00F7        STS_CC2500_WORTIME0	equ		0f7h;Low byte of WOR timer.
   40 00F8        STS_CC2500_PKTSTATUS	equ		0f8h;Current GDOx status and packet status.
   41 00F9        STS_CC2500_VCO_VC_DAC	equ		0f9h;Current setting from PLL calibration module.
   42 00FA        STS_CC2500_TXBYTES	equ		0fah;Underflow and number of bytes in the TX FIFO.
   43 00FB        STS_CC2500_RXBYTES	equ		0fbh;Overflow and number of bytes in the RX FIFO.
0044+  
0045+  
00046+              ;=========================================================
00047+              ;=========================================================
00048+              ;Define the Configuration Registers.
   49 0000        CFG_CC2500_IOCFG2	equ		00h; GDO2 output pin configuration.
   50 0001        CFG_CC2500_IOCFG1	equ		01h; GDO1 output pin configuration.
   51 0002        CFG_CC2500_IOCFG0	equ		02h; GDO0 output pin configuration.
   52 0003        CFG_CC2500_FIFOTHR	equ		03h; RX FIFO and TX FIFO thresholds.
   53 0004        CFG_CC2500_SYNC1	equ		04h; Sync word, high byte.
   54 0005        CFG_CC2500_SYNC0	equ		05h; Sync word, low byte.
   55 0006        CFG_CC2500_PKTLEN	equ		06h; Packet length.
   56 0007        CFG_CC2500_PKTCTRL1	equ		07h; Packet automation control.
   57 0008        CFG_CC2500_PKTCTRL0	equ		08h; Packet automation control.
   58 0009        CFG_CC2500_ADDR		equ		09h; Device address.
   59 000A        CFG_CC2500_CHANNR	equ		0ah; Channel number.
   60 000B        CFG_CC2500_FSCTRL1	equ		0bh; Frequency synthesizer control.
   61 000C        CFG_CC2500_FSCTRL0	equ		0ch; Frequency synthesizer control.
   62 000D        CFG_CC2500_FREQ2	equ		0dh; Frequency control word, high byte.
   63 000E        CFG_CC2500_FREQ1	equ		0eh; Frequency control word, middle byte.
   64 000F        CFG_CC2500_FREQ0	equ		0fh; Frequency control word, low byte.
   65 0010        CFG_CC2500_MDMCFG4	equ		10h; Modem configuration.
   66 0011        CFG_CC2500_MDMCFG3	equ		11h; Modem configuration.
   67 0012        CFG_CC2500_MDMCFG2	equ		12h; Modem configuration.
   68 0013        CFG_CC2500_MDMCFG1	equ		13h; Modem configuration.
   69 0014        CFG_CC2500_MDMCFG0	equ		14h; Modem configuration.
   70 0015        CFG_CC2500_DEVIATN	equ		15h; Modem deviation setting.
   71 0016        CFG_CC2500_MCSM2	equ		16h; Main Radio Control State Machine configuration.
   72 0017        CFG_CC2500_MCSM1	equ		17h; Main Radio Control State Machine configuration.
   73 0018        CFG_CC2500_MCSM0	equ		18h; Main Radio Control State Machine configuration.
   74 0019        CFG_CC2500_FOCCFG	equ		19h; Frequency Offset Compensation configuration.
   75 001A        CFG_CC2500_BSCFG	equ		1ah; Bit Synchronization configuration.
   76 001B        CFG_CC2500_AGCTRL2	equ		1bh; AGC control.
   77 001C        CFG_CC2500_AGCTRL1	equ		1ch; AGC control.
   78 001D        CFG_CC2500_AGCTRL0	equ		1dh; AGC control.
   79 001E        CFG_CC2500_WOREVT1	equ		1eh; High byte Event 0 timeout.
   80 001F        CFG_CC2500_WOREVT0	equ		1fh; Low byte Event 0 timeout.
   81 0020        CFG_CC2500_WORCTRL	equ		20h; Wake On Radio control.
   82 0021        CFG_CC2500_FREND1	equ		21h; Front end RX configuration.
   83 0022        CFG_CC2500_FREND0	equ		22h; Front end TX configuration.
   84 0023        CFG_CC2500_FSCAL3	equ		23h; Frequency synthesizer calibration.
   85 0024        CFG_CC2500_FSCAL2	equ		24h; Frequency synthesizer calibration.
   86 0025        CFG_CC2500_FSCAL1	equ		25h; Frequency synthesizer calibration.
   87 0026        CFG_CC2500_FSCAL0	equ		26h; Frequency synthesizer calibration.
   88 0027        CFG_CC2500_RCCTRL1	equ		27h; RC oscillator configuration.
   89 0028        CFG_CC2500_RCCTRL0	equ		28h; RC oscillator configuration.
   90 0029        CFG_CC2500_FSTEST	equ		29h; Frequency synthesizer calibration control.
   91 002A        CFG_CC2500_PTEST	equ		2ah; Production test.
   92 002B        CFG_CC2500_AGCTEST	equ		2bh; AGC test.
   93 002C        CFG_CC2500_TEST2	equ		2ch; Various test settings.
   94 002D        CFG_CC2500_TEST1	equ		2dh; Various test settings.
   95 002E        CFG_CC2500_TEST0	equ		2eh; Various test settings.
0096+  
00097+              ;=======================================================
00098+              ;=======================================================
   99 0000        D_SingleByte		equ		00h; The single byte write/read.
  100 0040        D_Burst			equ		40h; The burst write/read.
0101+  
00102              .endd
0103   
00104              ;*************************************************************
00105              ;
00106              .code
  107 0000 **** NEW ADDR ****  	org	000h;
  209 00108 0000 D029  	jmp	V_Reset;
  109 0010 **** NEW ADDR ****  	org	010h;
  211 00110 0010 D028  	jmp	V_IntPinInt;
  111 0014 **** NEW ADDR ****  	org	014h;
  213 00112 0014 D028  	jmp	V_IOC_DInt;
  113 0018 **** NEW ADDR ****  	org	018h;
  215 00114 0018 D051  	jmp	V_Tmr1Int;
  115 001C **** NEW ADDR ****  	org	01ch;
  217 00116 001C D05D  	jmp	V_PreDiverInt;
  117 0020 **** NEW ADDR ****  	org	020h;
  219 00118 0020 D028  	jmp	V_Tmr2Int;
  119 0024 **** NEW ADDR ****  	org	024h;
  221 00120 0024 D028  	jmp	V_KeyMatrixInt;
  121 0028 **** NEW ADDR ****  	org	028h;
00122              V_RFCInt:
00123              V_IntPinInt:
00124              V_IOC_DInt:
00125              V_Tmr2Int:
00126              V_KeyMatrixInt:
  228 00127 0028 F400  	rts;
00128              ;=============================================
00129              ;=============================================
00130              V_Reset:
  232 00131 0029 EE00  	fast;
  233 00132 002A C081  	call	F_ClrAllRAM;
  234 00133 002B C08A  	call	F_InitalPort;
  235 00134 002C C0CF  	call	F_InitalCC2500;
0135   
00136              ;	sie*	0;
00137              ;L_Loopssfd:
00138              ;	lds	R_RdAddrLow,10;
00139              ;	lds	R_RdAddrHigh,0;
00140              ;	call	F_ReadCC2500Reg;
00141              ;
00142              ;	nop;
00143              ;	nop;
00144              ;	jmp	L_Loopssfd
0145   
0146   
00147              L_MainLoop:
  249 00148 002D 6C01  	lda	R_KeyWakeDel;
  250 00149 002E B042  	jz	L_EntryHalt;
0150   
  252 00151 002F 6C79  	lda	R_KeyVal;
  253 00152 0030 B02D  	jz	L_MainLoop;
  254 00153 0031 588D  	lds	R_LoopSend,1;3;
  255 00154 0032 3F27  	ori*	R_Flags1,B_KeySend;
  256 00155 0033 5871  	lds	R_WrkReg1,0;
  257 00156 0034 0609  	lcp	R_RFLEDBuf,R_WrkReg1;
00157              L_LoopKeySend:
  259 00158 0035 6C79  	lda	R_KeyVal;
  260 00159 0036 6806  	sta	R_SendCommandLo;
  261 00160 0037 5807  	lds	R_SendCommandHi,0;
  262 00161 0038 C21F  	call	F_SendRFCommand;
0162   
  264 00163 0039 410D  	dec*	R_LoopSend;
  265 00164 003A A035  	jnz	L_LoopKeySend;
0165   
  267 00166 003B 58F1  	lds	R_WrkReg1,D_RFLED;
  268 00167 003C 0609  	lcp	R_RFLEDBuf,R_WrkReg1;
  269 00168 003D 3BD7  	andi*	R_Flags1,1101b;
  270 00169 003E 5879  	lds	R_KeyVal,0;
  271 00170 003F 5D04  	lds	R_TimerSendLo,D_TimerSendLo;
  272 00171 0040 5805  	lds	R_TimerSendHi,D_TimerSendHi;
  273 00172 0041 D02D  	jmp	L_MainLoop;
00173              ;=======================================
00174              L_EntryHalt:
  276 00175 0042 F510  	sca	10h;
  277 00176 0043 F780  	rf	80h;
  278 00177 0044 3F17  	ori*	R_Flags1,B_NormalStop;
  279 00178 0045 E908  	sie*	D_PreIntEnable;
  280 00179 0046 FF00  	halt;
0180   
  282 00181 0047 0000  	nop;
  283 00182 0048 0000  	nop;
  284 00183 0049 0000  	nop;
  285 00184 004A 5878  	lds	R_KeyStep,0;
  286 00185 004B 3BE7  	andi*	R_Flags1,1110b;
  287 00186 004C 5B01  	lds	R_KeyWakeDel,D_KeyWakeDel;
  288 00187 004D E27F  	tmsx	001111111b;   15.625ms interrupt.
  289 00188 004E F680  	sf	80h;          Enable the re-load function.
  290 00189 004F E90A  	sie*	D_Tmr1IntEnable+D_PreIntEnable;
  291 00190 0050 D02D  	jmp	L_MainLoop;
00191              ;*************************************************************
00192              ;V: Vector Name: V_Tmr1Int.
00193              ;V: Describe:
00194              ;V:   15.625ms Interrupt for key scan or delay time base.
00195              ;V:
00196              ;*************************************************************
00197              V_Tmr1Int:
  299 00198 0051 6802  	sta	R_TempAcc;
  300 00199 0052 4A03  	maf	R_TempStatus;
  301 00200 0053 7890  	mwr	R_TempWrk,R_WrkReg1;
0201   
  303 00202 0054 C0A4  	call	F_ScanKey;
  304 00203 0055 6C01  	lda	R_KeyWakeDel;
  305 00204 0056 B058  	jz	L_Tmr1IntRet;
0205   
  307 00206 0057 4101  	dec*	R_KeyWakeDel;
00207              L_Tmr1IntRet: