isr.c

一个比较好用的TW2835音视频芯片开发板的程序,

#include	"hdr.h"
//#include	"isr.h"
 
//==================================================================================
//						Interrupt service routine function description
//==================================================================================
void ExeIsrEx0(void) interrupt 0		//... mse clock interrupt
{
//*
	U8 _t1_;
	
	EX0 = 0;

	if(mse_cnt_clk > 0 && mse_cnt_clk < 9)
	{
		if((mse_rdata[0] & 0x01) != 0)
			MSE_DAT = 1;
		else
			MSE_DAT = 0;

		mse_rdata[0] >>= 1;
	}
	else
	{
		if(MSE_DAT == 0)
			_t1_ = 0x00;
		else
			_t1_ = 0x80;
	
		if((mse_cnt_clk >= 13) && (mse_cnt_clk <= 20))
		{
			mse_rdata[0] >>= 1;
			mse_rdata[0] |= _t1_;  
		}
		else if((mse_cnt_clk >= 24) &&( mse_cnt_clk <= 31))
		{
			mse_rdata[1] >>= 1;
			mse_rdata[1] |= _t1_;  
		}
		else if((mse_cnt_clk >= 35) &&( mse_cnt_clk <= 42))
		{
			mse_rdata[2] >>= 1;
			mse_rdata[2] |= _t1_;  
		}
		else if((mse_cnt_clk >= 46) && (mse_cnt_clk <= 53))
		{
			mse_rdata[3] >>= 1;
			mse_rdata[3] |= _t1_;  
		}
	}

	if(mse_cnt_clk < 55){
		mse_cnt_clk++;
		b_mse_rd_done = 0;
		
		IE0 = 0;			//... clear interrupt edge flag(-> pending flag)
		EX0 = 1;
	}
	else{		//... mse_cnt_clk == 54
		b_mse_rd_done = 1;
	}
	//	*/
}
//==================================================================================
void ExeIsrEx1(void) interrupt 2		//... VSENC signal interrupt
{
	EX1 = 0;
//	U8 _t1_, _t2_;
//	
//	EX1 = 0;
//
////*
//	b_cmn_dtct_vs = 1;
//
//	if(b_cmn_jp_vdo == VDO_NTSC){
//		_t1_ = 60;
//		_t2_ = 6;//12;
//	}
//	else{
//		_t1_ = 50;
//		_t2_ = 5;//10;
//	}
//	
//	if((cmn_cnt_vs&0x01) == 0)	b_cmn_cnt_fld = 1;
//	if(cmn_cnt_vs > 0){
//		cmn_cnt_vs--;
//		if(cmn_cnt_vs == (_t1_>>1)){
//			b_cmn_cnt_05s = 1;
////			b_cmn_cnt_01s = 1;
//		}
//		if(cmn_cnt_vs == cmn_cnt_vs_sub){
////			b_cmn_cnt_02s = 1;
//			b_cmn_cnt_01s = 1;
//			b_cmn_cnt_tgl ^= 1;
//
//			if(cmn_cnt_vs > _t2_)	cmn_cnt_vs_sub = cmn_cnt_vs - _t2_;
//		}
//		if(b_cmn_cnt_tgl == 0)	b_cmn_cnt_02s = 1;
//	}
//	else{
//		cmn_cnt_vs = _t1_;
////		cmn_cnt_vs_sub = _t2_<<2;
//		cmn_cnt_vs_sub = _t1_-_t2_;
//		b_cmn_cnt_1s = 1;
//		b_cmn_cnt_05s = 1;
//		b_cmn_cnt_02s = 1;
//		b_cmn_cnt_01s = 1;
//		b_cmn_cnt_tgl = 0;
//	}
//	//	*/

	IE1 = 0;			//... clear interrupt edge flag(-> pending flag)
	EX1 = 1;
}
//==================================================================================
void ExeIsrEx2(void) interrupt 8//7
{
////	SetBit(T2MOD,BIT4);			//... clear interrupt flag(-> pending flag)
////	ClearBit(EXIF,BIT4);			//... clear interrupt flag(-> pending flag)
//	EX2 = 0;

	U8 _t1_, _t2_;
	
	EX2 = 0;

	b_cmn_dtct_vs = 1;

	if(b_cmn_jp_vdo == VDO_NTSC){
		_t1_ = 60;
		_t2_ = 6;//12;
	}
	else{
		_t1_ = 50;
		_t2_ = 5;//10;
	}
	
//	if((cmn_cnt_vs&0x01) == 0)	b_cmn_cnt_fld = 1;
	if(cmn_cnt_vs > 0){
		cmn_cnt_vs--;
		if(cmn_cnt_vs == (_t1_>>1)){
			b_cmn_cnt_05s = 1;
//			b_cmn_cnt_01s = 1;
		}
		if(cmn_cnt_vs == cmn_cnt_vs_sub){
//			b_cmn_cnt_02s = 1;
			b_cmn_cnt_01s = 1;
			b_cmn_cnt_tgl ^= 1;

			if(cmn_cnt_vs > _t2_)	cmn_cnt_vs_sub = cmn_cnt_vs - _t2_;
		}
		if(b_cmn_cnt_tgl == 0)	b_cmn_cnt_02s = 1;
	}
	else{
		cmn_cnt_vs = _t1_;
//		cmn_cnt_vs_sub = _t2_<<2;
		cmn_cnt_vs_sub = _t1_-_t2_;
		b_cmn_cnt_1s = 1;
		b_cmn_cnt_05s = 1;
		b_cmn_cnt_02s = 1;
		b_cmn_cnt_01s = 1;
		b_cmn_cnt_tgl = 0;
	}

//	b_cmn_fld_evn = 1;

//P2_4 ^= 1;//0xff;

	EX2 = 1;
}
//==================================================================================
void ExeIsrEx3(void) interrupt 9//8
{
////	SetBit(T2MOD,BIT5);			//... clear interrupt flag(-> pending flag)
////	ClearBit(EXIF,BIT5);			//... clear interrupt flag(-> pending flag)
//	EX3 = 0;

	U8 _t1_, _t2_;
	
	EX3 = 0;

	b_cmn_dtct_vs = 1;

	if(b_cmn_jp_vdo == VDO_NTSC){
		_t1_ = 60;
		_t2_ = 6;//12;
	}
	else{
		_t1_ = 50;
		_t2_ = 5;//10;
	}
	
//	if((cmn_cnt_vs&0x01) == 0)	b_cmn_cnt_fld = 1;
	if(cmn_cnt_vs > 0){
		cmn_cnt_vs--;
		if(cmn_cnt_vs == (_t1_>>1)){
			b_cmn_cnt_05s = 1;
//			b_cmn_cnt_01s = 1;
		}
		if(cmn_cnt_vs == cmn_cnt_vs_sub){
//			b_cmn_cnt_02s = 1;
			b_cmn_cnt_01s = 1;
			b_cmn_cnt_tgl ^= 1;

			if(cmn_cnt_vs > _t2_)	cmn_cnt_vs_sub = cmn_cnt_vs - _t2_;
		}
		if(b_cmn_cnt_tgl == 0)	b_cmn_cnt_02s = 1;
	}
	else{
		cmn_cnt_vs = _t1_;
//		cmn_cnt_vs_sub = _t2_<<2;
		cmn_cnt_vs_sub = _t1_-_t2_;
		b_cmn_cnt_1s = 1;
		b_cmn_cnt_05s = 1;
		b_cmn_cnt_02s = 1;
		b_cmn_cnt_01s = 1;
		b_cmn_cnt_tgl = 0;
	}

	b_cmn_cnt_fld = 1;

	b_cmn_fld_od = 1;

//P2_5 ^= 1;//0xff;

	EX3 = 1;
}
//==================================================================================
void ExeIsrEx4(void) interrupt 10//9
{
//	SetBit(T2MOD,BIT6);			//... clear interrupt flag(-> pending flag)
//	ClearBit(EXIF,BIT6);			//... clear interrupt flag(-> pending flag)
	EX4 = 0;

	b_cmn_irq = 1;

	EX4 = 1;
}
//==================================================================================
void ExeIsrEx5(void) interrupt 11//10
{
//	SetBit(T2MOD,BIT7);			//... clear interrupt flag(-> pending flag)
//	ClearBit(EXIF,BIT7);			//... clear interrupt flag(-> pending flag)
	EX5 = 0;

	EX5 = 1;
}
//==================================================================================
void ExeIsrTmr0(void) interrupt 1
{
	U8 _t1_, _t2_;
	
	ET0 = 0;		//... disable interrupt timer0
//	TR0 = 0;		//... stop count for timer0

//... 1. 12M[Hz] : 1[usec] = 40M[Hz] : 1/x[usec] (-> x = 3/10 [usec])
/*
//... 2. 3/10 [usec] : 1[step] = 1/300[sec] : x[step] (-> x = 100000/9 [step] = 11,111.11)
//... 3. 0xffff - 0x2b67(-> 11,111.11) = 0xd498
//... 4. 0xffff - 0x2b3f = 0xd4c0 (after checking 1 sec(about 999.98 ms) with oscilloscope)

//... To use % in interrupt sub routine takes too long time(about 2 ~ 3 mse clock period). So not good.

	TH0 = 0xd4;
	TL0 = 0xc0;

	if(cmn_cnt_tmr < 63299)	cmn_cnt_tmr++;
	else	cmn_cnt_tmr = 0;

	if(b_jp_video == NTSC){
		if((cmn_cnt_tmr%5) == 0)	b_cmn_dtct_vs = 1;
		if((cmn_cnt_tmr%10) == 0)	b_cmn_cnt_fld = 1;
	}
	else{
		if((cmn_cnt_tmr%6) == 0)	b_cmn_dtct_vs = 1;
		if((cmn_cnt_tmr%12) == 0)	b_cmn_cnt_fld = 1;
	}
	if((cmn_cnt_tmr%150) == 0)
		b_cmn_cnt_05s = 1;
	if((cmn_cnt_tmr%300) == 0)								//... 999.98 [ms]
		b_cmn_cnt_1s = 1;
//	*/
//*
	if(b_cmn_jp_vdo == VDO_NTSC){
//... 2. 3/10 [usec] : 1[step] = 1/60[sec] : x[step] (-> x = 0xd903 [step])
//... 3. 0xffff - 0xd903 = 0x26fc
		TH0 = 0x26;
		TL0 = 0xfc;
		_t1_ = 60;

		b_cmn_dtct_vs = 1;
	}
	else{
//... 2. 3/10 [usec] : 1[step] = 1/50[sec] : x[step] (-> x = 0x0001046a [step])
//... 3. 1st:0xffff - 0x0000 = 0xffff
//...		2nd:0xffff - 0x046a = 0xfb95
		_t1_ = 50;
		if(b_cmn_cnt_tgl == 0){
			b_cmn_cnt_tgl = 1;

			TH0 = 0x00;
			TL0 = 0x00;
			b_cmn_dtct_vs = 1;
		}
		else{
			b_cmn_cnt_tgl = 0;

			TH0 = 0xfb;
			TL0 = 0x95;
		}
	}

//	if(b_cmn_dtct_vs == 1){
//		if(cmn_cnt_vs > 0){
//			cmn_cnt_vs--;
//			if(cmn_cnt_vs == (_t1_>>1))	b_cmn_cnt_05s = 1;
//		}
//		else{
//			cmn_cnt_vs = _t1_;
//			b_cmn_cnt_1s = 1;
//			b_cmn_cnt_05s = 1;
//		}
//	}
	if(b_cmn_dtct_vs == 1){
		if(cmn_cnt_vs > 0){
			cmn_cnt_vs--;
			if(cmn_cnt_vs == (_t1_>>1)){
				b_cmn_cnt_05s = 1;
			}
			if(cmn_cnt_vs == cmn_cnt_vs_sub){
				b_cmn_cnt_01s = 1;
				b_cmn_cnt_tgl ^= 1;
	
				if(cmn_cnt_vs > _t2_)	cmn_cnt_vs_sub = cmn_cnt_vs - _t2_;
			}
			if(b_cmn_cnt_tgl == 0)	b_cmn_cnt_02s = 1;
		}
		else{
			cmn_cnt_vs = _t1_;
			cmn_cnt_vs_sub = _t1_-_t2_;
			b_cmn_cnt_1s = 1;
			b_cmn_cnt_05s = 1;
			b_cmn_cnt_02s = 1;
			b_cmn_cnt_01s = 1;
			b_cmn_cnt_tgl = 0;
		}
	}
//	*/
	TF0 = 0;		//... clear interrupt flag
//	TR0 = 1;		//... start count for timer0
	ET0 = 1;		//... enable interrupt timer0
}
//==================================================================================
void ExeIsrTmr1(void) interrupt 3
{
	ET1 = 0;		//... disable interrupt timer1
//	TR1 = 0;		//... stop count for timer1

	TF1 = 0;		//... clear interrupt flag
//	TR1 = 1;		//... start count for timer1
	ET1 = 1;		//... enable interrupt timer1
}
//==================================================================================
void ExeIsrTmr2(void) interrupt 5
{
	ET2 = 0;		//... disable interrupt timer2
//	TR2 = 0;		//... stop count for timer2

	TF2 = 0;		//... clear interrupt flag
//	TR2 = 1;		//... start count for timer2
	ET2 = 1;		//... enable interrupt timer2
}
//==================================================================================
//==================================================================================
//... initialize Interrupt
void InitIsr(void)
{
//... interrupt priority
//... PS = 0;	PT1 = 0;	PX1 = 0;	PT0 = 0;	PX0 = 0;
	IP = 0x00;

//... interrupt enable
//... EA = 0;	ES = 0;	ET1 = 0;	EX1 = 1;	ET0 = 0;	EX0 = 1;
	IE = 0x00;

	TMOD = 0x11;

	T2MOD = 0xf0;		//... clear interrupt flag(-> IE2 to IE5: pending flag) automatically by HC2 to HC5

//... interrupt type
//... IT: 1 (falling edge trigger), IT : 0 (low level trigger)
	IT0=1;
	IT1=1;

//... external interrupt (int3, int2)
/* XICON */
	PX5 = 0;		//... polarity
	EX5 = 0;		//... enable

	PX4 = 0;		//... polarity
	EX4 = 0;		//... enable

	PX3 = 0;		//... polarity
	EX3 = 0;		//... enable
//	IE3 = 0;		//... status
//	IT3 = 1;		//... type
	
	PX2 = 0;		//... polarity
	EX2 = 0;		//... enable
//	IE2 = 0;		//... status
//	IT2 = 1;		//... type
}
//==================================================================================
//void	StrtIsr(void)
//{
//}
////==================================================================================
//void	EnIsr(U32 _isr)
//{
//	rINTMSK &= ~(_isr);										//... disable mask bit for _isr
//}
////==================================================================================
//void	DisIsr(void)
//{
//	rINTMSK = 0xffffffff;									//... enable all mask
//}
////==================================================================================