mux.v

来自「每路输入数据与输出数据均为4位2进制数」· Verilog 代码 · 共 20 行

/*8-1 MUX*/
module SELE (A,SEL,F);
    input [7:0]A;
    input [2:0]SEL;
    output F;
    wire SEL2_NOT,SEL1_NOT,SEL0_NOT;
    wire [7:0]AND;
    not U2 (SEL2_NOT,SEL[2]),
        U1 (SEL1_NOT,SEL[1]),
        U0 (SEL0_NOT,SEL[0]);
    and U3 (AND[0],A[0],SEL0_NOT,SEL1_NOT,SEL2_NOT),
        U4 (AND[1],A[1],SEL[0],SEL1_NOT,SEL2_NOT),
        U5 (AND[2],A[2],SEL0_NOT,SEL[1],SEL2_NOT),
        U6 (AND[3],A[3],SEL[0],SEL[1],SEL2_NOT),
        U7 (AND[4],A[4],SEL0_NOT,SEL1_NOT,SEL[2]),
        U8 (AND[5],A[5],SEL[0],SEL1_NOT,SEL[2]),
        U9 (AND[6],A[6],SEL0_NOT,SEL[1],SEL[2]),
        U10 (AND[7],A[7],SEL[0],SEL[1],SEL[2]); 
    or U11 (F,AND[0],AND[1],AND[2],AND[3],AND[4],AND[5],AND[6],AND[7]);
endmodule