hw_at2041_api.c

1、基于韩国at2041芯片开发的Linux环境的DVR代码。 2、以原来代码进行了修改。 3、主要修改网络通讯出现异常问题处理 4、硬盘覆盖录像不起作用

        ioctl(fd_at2041, WRITE_Rx_FIFO, &hscale_mode);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &vscale_mode);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void encode_region_info(UNS16 ch_id, UNS16 h_offset, UNS16 v_offset, UNS16 h_mbsize, UNS16 v_mbsize)
{
        /* ch_id    : channel ID
         * h_offset : horizontal offset (16-pel unit), default is 0
         * v_offset : vertical offset (2-line unit), default is 0
         * h_mbsize : horizontal MB size (16-pel unit), default is 45
         * v_mbsize : vertical MB size (16-line unit), default is 30
         */
        rx_id = RxID(GID_EVC, ch_id, PID_EVC_REC_RGN, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &h_offset);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &v_offset);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &h_mbsize);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &v_mbsize);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void recoding_frame_rate_control(UNS16 ch_id, UNS16 input_frame_number, UNS16 rec_frame_number)
{
	/* ch_id : channel ID
	 * input_frame_number : the number of input frames
	 *                      1 ~ 255, default is 1
	 * rec_frame_number   : the number of frames to be recorded out of input frames
	 *                      0 ~ number of input frame, default is 1
	 */

        rx_id = RxID(GID_EVC, ch_id, PID_EVC_FPS_CTRL, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &input_frame_number);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rec_frame_number);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void motionless_record_mode(UNS16 ch_id, UNS16 mode)
{
        /* mode : '0' normal record, '1' not record, default is '0' */
        rx_id = RxID(GID_EVC, ch_id, PID_EVC_MD_MODE, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &mode);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void motion_detection_parameter(UNS16 ch_id, UNS16 sensitivity, UNS16 pel_diff_threshold, 
	UNS16 diff_pel_count_threshold, UNS16 motion_mb_count_threshold, 
	UNS16 motionless_frame_count_threshold)
{
	/* ch_id : channel ID
	 * sensitivity : sensitivity '0'(more sensitive) ~ '7'(less sensitive), default is '2'
	 * pel_diff_threshold : pixel difference threshold, '0' ~ '63', default is 32
	 * diff_pel_count_threshold : different pixel count threshold
	 *                            '0' ~ '127', default is '32'
	 * motion_mb_count_threshold : motion MB count threshold
	 *                            '0' ~ '255', default is '5'
	 * motionless_frame_count_threshold : motion-less frame count threshold
	 *                                    '0' ~ '255', default is '5'
	 */
        rx_id = RxID(GID_EVC, ch_id, PID_EVC_MD_PARM, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &sensitivity);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &pel_diff_threshold);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &diff_pel_count_threshold);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &motion_mb_count_threshold);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &motionless_frame_count_threshold);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void motion_detection_area_bitmap(UNS16 ch_id, UNS16 *bitmap)
{
	/* ch_id : channel ID
	 * bitmap : 1 bit is assigned to 2x2MBs and 3 bytes are assigned to 2 slices.
	 *         The MS bit of the first byte is aligned to the left-top 2x2MBs of the input video
	 */
	 UNS16 ii;

       rx_id = RxID(GID_EVC, ch_id, PID_EVC_MD_AREA, W_FLAG);
       ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
       for (ii = 0; ii < 54; ii ++) {
	       ioctl(fd_at2041, WRITE_Rx_FIFO, &bitmap[ii]);	
       }
       ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

/* Encoder audio parameters */
void audio_encode_standard(UNS16 standard)
{
	/* standard : '1' ADPCM, '2' MPEG-1 layer 2, '3' MPEG-1 layer 3, '9' ADPCM STREO
	 *            default is '1'
	 */
        rx_id = RxID(GID_EA, 0x00, PID_EA_STD, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &standard);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

#if 0//not use
void audio_input_channel_number(UNS16 number)
{
	/* number : '1' ~ '16', default is '4'
	 *          Multi-channel encoding is supported only if the
	 *          encoding standard is ADPCM
	 */
        rx_id = RxID(GID_EA, 0x00, PID_EA_CH_SIZE, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &number);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}
#endif

void audio_input_format(UNS16 format, UNS16 bits, UNS16 delay_mode)
{
	/* format : audio input format
	 *          '0' I2S mode, '1' left justified mode, '2' u-Law PCM mode,
	 *          '3' a-Law PCM mode, '4' linear PCM mode, default is '2'
	 * bits : bits per sample x the number of the input channel
	 *        '0' 8-bit, '1' 16-bit, '4' 32-bit, '5' 64-bit,
	 *        '6' 128-bit, default is '4'
	 * delay_mode : delay mode, '0' no delay, '1' 1 bit delay, default is 0
	 */
        rx_id = RxID(GID_EA, 0x00, PID_EA_FMT, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &format);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &bits);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &delay_mode);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void enc_audio_clock_inversion(UNS16 type)
{
	/* type : '0' use input clock, '1' use inverted clock, default is '0'
	 *        This parameter is the same one that is in the audio decoder
	 */
        rx_id = RxID(GID_EA, 0x00, PID_EA_CLK_INV, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &type);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void enc_audio_interface_mode(UNS16 mode)
{
	/* mode : '0' master mode, '1' slave mode, default is '0'
	 *        This parameter is the same one that is in the audio decoder 
	 */
        rx_id = RxID(GID_EA, 0x00, PID_EA_IF_MODE, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &mode);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void enc_audio_frame_sync_width(UNS16 width)
{
	/* width : '0' ~ '1024', default is '0'
	 *         This parameter is the same one that is in the audio decoder 
	 */
        rx_id = RxID(GID_EA, 0x00, PID_EA_FSYNC_WIDTH, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &width);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

/* Encoder audio channel parameters */
void audio_restart(UNS16 ch_id)
{
        rx_id = RxID(GID_EAC, ch_id, PID_EAC_RESTART, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void audio_pause(UNS16 ch_id)
{
        rx_id = RxID(GID_EAC, ch_id, PID_EAC_PAUSE, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void audio_physical_chid_assign(UNS16 ch_id, UNS16 cid)
{
	/* ch_id : channel ID
	 * cid : physical channel ID, '0' ~ '15'
	 */
        rx_id = RxID(GID_EAC, ch_id, PID_EAC_PHY_CID, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &cid);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

/* decoder system parameters */
void video_decoder_start(void) 
{
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_START, W_FLAG);
	write_parm(rx_id, 0x0003);
}

void video_decoder_stop(void) 
{
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_STOP, W_FLAG);
	write_parm(rx_id, 0x0003);
}

void dec_resume(void)
{
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_RESUME, W_FLAG);
    ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);

    ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}
void video_decoder_buffer_reset(void)
{
	S32 dummy;

	ioctl(fd_at2041, AT2041_DEC_RESET_BUFFER, &dummy);
}


void input_stream_format(UNS16 format)
{
	/* format : '1' ES or Data, '2' PES or PS, '3' TS, default is '1'
	 */
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_STR_FMT, W_FLAG);
	write_parm(rx_id, format);
}

void sync_lock_count_number(UNS16 number)
{
	/* number : '0' ~ '7', default is '3'
	 *          This is valid only if the input stream format is TS
	 */
	rx_id = RxID(GID_DEC, 0x00, PID_DEC_SLOCK_NUM, W_FLAG);
	write_parm(rx_id, number);
}

void decode_mode(UNS16 mode)
{
        /* mode : '0' real time mode(use time stamp)
         *        '1' non-real time mode(not use time stamp)
         *         default is real time mode
         */
        rx_id = RxID(GID_DEC, 0x00, PID_DEC_MODE, W_FLAG);
        write_parm(rx_id, mode);
}

/* decoder video parameters */
void output_video_format(UNS16 format)
{
        /* format : '0' NTSC, '1' PAL, default is '0'   */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FMT, W_FLAG);
        write_parm(rx_id, format);
}

void output_video_clock_inversion(UNS16 mode)
{
	/* mode : '0' use input clock
	 *        '1' use inverted input clock
	 *        default is '0'
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_CLK_INV, W_FLAG);
        write_parm(rx_id, mode);
}

void video_interface_mode(UNS16 mode)
{
	/* mode : '0' master, '1' slave, default is '0' */
        rx_id = RxID(GID_DV, 0x00, PID_DV_SLAVE, W_FLAG);
        write_parm(rx_id, mode);
}

void dec_vertical_offset_mode(UNS16 ef_voffset, UNS16 of_voffset)
{
	/* ef_voffset : vertical offset for even field, default is 284
	 * of_voffset : vertical offset for odd field, default is 21
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_VOFF, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &ef_voffset);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &of_voffset);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void dec_field_sync_mode(UNS16 mode)
{
	/* mode : '0' generate field sync using the 'first field decision parameter'
	 *        '1' use field sync input
	 *        default is '0'
	 *        This is vlaid only if slave mode is 1
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FSYNC_M, W_FLAG);
        write_parm(rx_id, mode);
}

void first_field_decision_parameter(UNS16 value)
{
	/* This is valid only if the field sync mode is 0.
	 * if the number of clock cycles between the start of vertical sync 
	 * and the start of horizontal sync falling is less than or equal this value,
	 * the next field is the first field.
	 *
	 * default is 128
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FSYNC_P, W_FLAG);
        write_parm(rx_id, value);
}

void horizontal_sync_control(UNS16 hsync_start_position, UNS16 hsync_end_position, UNS16 hsync_to_hvalid_end_cycle)
{
	/* hsync_start_position : horizontal sync start position
	 *                        default is 28
	 * hsync_end_position : horizontal sync end position
	 *                      default is 159
	 * hsync_to_hvalid_end_cycle : hsync to hvalid end cycle
	 *				 default is 1440 
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_HSYNC_CTRL, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &hsync_start_position);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &hsync_end_position);
	  ioctl(fd_at2041, WRITE_Rx_FIFO, &hsync_to_hvalid_end_cycle);	
        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void vertical_sync_control(UNS16 start_line_number_ff, UNS16 end_line_number_ff, 
	UNS16 transition_position_ff, UNS16 start_line_number_sf, 
	UNS16 end_line_number_sf, UNS16 transition_position_sf)
{
	/* start_line_number_ff   : vertical sync start line number of the first field
	 *                          default is 3
	 * end_line_number_ff     : vertical sync end line number of the first field
	 *                          default is 7
	 * transition_position_ff : vertical sync transition position of the first field,
	 *                          this value means the offset cycles from the end of
	 *                          horizontal valid to the vercical sync transition position
	 *                          default is 90
	 * start_line_number_sf   : vertical sync start line number of the second field
	 *                          default is 265
	 * end_line_number_sf     : vertical sync end line number of the second field
	 *                          default is 268
	 * transition_position_sf : vertical sync transition position of the second field
	 *                          default is 855
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_VSYNC_CTRL, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &start_line_number_ff);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &end_line_number_ff);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &transition_position_ff);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &start_line_number_sf);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &end_line_number_sf);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &transition_position_sf);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void field_sync_control(UNS16 start_line_number_ff, UNS16 start_line_number_sf, 
			UNS16 transition_position)
{
	/* start_line_number_ff : the first field start line number
	 *                        default is 3
	 * start_line_number_sf : the second field start line number
	 *                        default is 265
	 * transition_position  : field sync transition position
	 *                        this value means the offset cycles from the end of horizontal
	 *                        valid to the field sync transition position
	 *                        default is 31
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_FSYNC_CTRL, W_FLAG);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &rx_id);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &start_line_number_ff);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &start_line_number_sf);
        ioctl(fd_at2041, WRITE_Rx_FIFO, &transition_position);

        ioctl(fd_at2041, END_OF_WRITE_Rx_FIFO);
}

void video_output_sync_polarity(UNS16 hvalid, UNS16 hsync, UNS16 vvalid, UNS16 vsync, UNS16 fsync)
{
	/* hvalid : horizontal valid polarity
	 *          '0' active low, '1' active high, default is '1'
	 * hsync  : horizontal sync polarity
	 *          '0' active high, '1' active low, default is '0'
	 * vvalid : vertical valid polarity
	 *          '0' active low, '1' active high, default is '1'         
	 * vsync  : vertical sync polarity
	 *          '0' active high, '1' active low, default is '0'
	 * fsync  : field sync value of the first field
	 *          default is '0'
	 */
        rx_id = RxID(GID_DV, 0x00, PID_DV_SYNC_POL, W_FLAG);
	rx_data = (fsync << 4) | (vsync << 3) | (vvalid << 2) | (hsync << 1) | hvalid;
        write_parm(rx_id, rx_data);