plxchip.c

PCI9054RDK-LITE开发板的原程序

            break;

        case IopSpace2:
            *pBarIndex        = 4;
            *pOffset_RegRemap = PCI9030_REMAP_SPACE2;
            break;

        case IopSpace3:
            *pBarIndex        = 5;
            *pOffset_RegRemap = PCI9030_REMAP_SPACE3;
            break;

        default:
            *pBarIndex = (U8)-1;
            DebugPrintf(("ERROR - Invalid Space\n"));
            break;
    }
}




/******************************************************************************
 *
 * Function   :  PlxChipPostCommonBufferProperties
 *
 * Description:  Post the common buffer properties to the device
 *
 ******************************************************************************/
VOID
PlxChipPostCommonBufferProperties(
    DEVICE_EXTENSION *pdx,
    U32               PhysicalAddress,
    U32               Size
    )
{
    // Nothing to do for this chip
}




/******************************************************************************
 *
 * Function   :  PlxIsPowerLevelSupported
 *
 * Description:  Verify that the power level is supported
 *
 ******************************************************************************/
BOOLEAN
PlxIsPowerLevelSupported(
    DEVICE_EXTENSION *pdx,
    PLX_POWER_LEVEL   PowerLevel
    )
{
    U32 RegisterValue;


    // Check if New capabilities are enabled
    if (PlxIsNewCapabilityEnabled(
            pdx,
            CAPABILITY_POWER_MANAGEMENT
            ) == FALSE)
    {
        return FALSE;
    }

    // Verify that the Power State is supported
    switch (PowerLevel)
    {
        case D0:
        case D3Hot:
            break;

        case D1:
        case D2:
            // Get the Power Control/Status
            PLX_PCI_REG_READ(
                pdx,
                PCI9030_PM_CAP_ID,
                &RegisterValue
                );

            if ((PowerLevel == D1) && !(RegisterValue & (1 << 25)))
                return FALSE;

            if ((PowerLevel == D2) && !(RegisterValue & (1 << 26)))
                return FALSE;
            break;

        case D0Uninitialized:    // D0Uninitialized cannot be set by software
        case D3Cold:             // D3Cold cannot be set by software
        default:
            return FALSE;
    }

    return TRUE;
}




/******************************************************************************
 *
 * Function   :  PlxIsNewCapabilityEnabled
 *
 * Description:  Verifies access to the new Capabilities registers
 *
 ******************************************************************************/
BOOLEAN
PlxIsNewCapabilityEnabled(
    DEVICE_EXTENSION *pdx,
    U8                CapabilityToVerify
    )
{
    U32 RegisterValue;
    U32 RegisterPmCapability;
    U32 RegisterHsCapability;
    U32 RegisterVpdCapability;


    // Check if New capabilities are enabled
    PLX_PCI_REG_READ(
        pdx,
        PCI9030_COMMAND,
        &RegisterValue
        );

    if ((RegisterValue & (1 << 20)) == 0)
        return FALSE;

    // Get capabilities pointer
    PLX_PCI_REG_READ(
        pdx,
        PCI9030_CAP_PTR,
        &RegisterValue
        );

    // Mask non-relevant bits
    RegisterValue = RegisterValue & 0xFF;

    if (RegisterValue == 0)
        return FALSE;

    // Get PM capabilities pointer
    PLX_PCI_REG_READ(
        pdx,
        PCI9030_PM_CAP_ID,
        &RegisterPmCapability
        );

    // Mask non-relevant bits
    RegisterPmCapability = (RegisterPmCapability >> 8) & 0xFF;

    // Get HS capabilities pointer
    PLX_PCI_REG_READ(
        pdx,
        PCI9030_HS_CAP_ID,
        &RegisterHsCapability
        );

    // Mask non-relevant bits
    RegisterHsCapability = (RegisterHsCapability >> 8) & 0xFF;

    // Get VPD capabilities pointer
    PLX_PCI_REG_READ(
        pdx,
        PCI9030_VPD_CAP_ID,
        &RegisterVpdCapability
        );

    // Mask non-relevant bits
    RegisterVpdCapability = (RegisterVpdCapability >> 8) & 0xFF;

    if (CapabilityToVerify & CAPABILITY_POWER_MANAGEMENT)
    {
        if ( (RegisterValue         != PCI9030_PM_CAP_ID) &&
             (RegisterPmCapability  != PCI9030_PM_CAP_ID) &&
             (RegisterHsCapability  != PCI9030_PM_CAP_ID) &&
             (RegisterVpdCapability != PCI9030_PM_CAP_ID) )
        {
            return FALSE;
        }
    }

    if (CapabilityToVerify & CAPABILITY_HOT_SWAP)
    {
        if ( (RegisterValue         != PCI9030_HS_CAP_ID) &&
             (RegisterPmCapability  != PCI9030_HS_CAP_ID) &&
             (RegisterHsCapability  != PCI9030_HS_CAP_ID) &&
             (RegisterVpdCapability != PCI9030_HS_CAP_ID) )
        {
            return FALSE;
        }
    }

    if (CapabilityToVerify & CAPABILITY_VPD)
    {
        if ( (RegisterValue         != PCI9030_VPD_CAP_ID) &&
             (RegisterPmCapability  != PCI9030_VPD_CAP_ID) &&
             (RegisterHsCapability  != PCI9030_VPD_CAP_ID) &&
             (RegisterVpdCapability != PCI9030_VPD_CAP_ID) )
        {
            return FALSE;
        }
    }

    return TRUE;
}




/******************************************************************************
 *
 * Function   :  PlxHiddenRegisterRead
 *
 * Description:  Read a hidden register
 *
 ******************************************************************************/
U32
PlxHiddenRegisterRead(
    DEVICE_EXTENSION *pdx,
    U16               offset
    )
{
    S8  i;
    U32 RegisterPm;
    U32 RegisterSave;
    U32 RegisterDataScale;
    U32 RegisterDataSelect;


    if ((offset != PCI9030_PM_DATA_SELECT) &&
        (offset != PCI9030_PM_DATA_SCALE))
    {
        return (U32)-1;
    }

    // Save the PM register
    PLX_PCI_REG_READ(
        pdx,
        PCI9030_PM_CSR,
        &RegisterSave
        );

    // Turn off PME status so we don't clear it
    RegisterSave &= ~(1 << 15);

    RegisterDataScale  = 0;
    RegisterDataSelect = 0;

    i = 0;
    while (i != -1)
    {
        // Clear Data_Select
        RegisterPm = RegisterSave & ~(0x7 << 9);

        // Setup Data_Select
        RegisterPm = RegisterPm | (i << 9);

        // Write to the PM Control Register
        PLX_PCI_REG_WRITE(
            pdx,
            PCI9030_PM_CSR,
            RegisterPm
            );

        // Get the result
        PLX_PCI_REG_READ(
            pdx,
            PCI9030_PM_CSR,
            &RegisterPm
            );

        // Build the hidden registers & increment to next selection
        switch (i)
        {
            case 0:
                i = 3;
                RegisterDataSelect |= (RegisterPm >> 24) << 0;
                RegisterDataScale  |= ((RegisterPm >> 13) & 0x3) << 0;
                break;

            case 3:
                i = 4;
                RegisterDataSelect |= (RegisterPm >> 24) << 8;
                RegisterDataScale  |= ((RegisterPm >> 13) & 0x3) << 2;
                break;

            case 4:
                i = 7;
                RegisterDataSelect |= (RegisterPm >> 24) << 16;
                RegisterDataScale  |= ((RegisterPm >> 13) & 0x3) << 4;
                break;

            case 7:
                i = -1;
                RegisterDataSelect |= (RegisterPm >> 24) << 24;
                RegisterDataScale  |= ((RegisterPm >> 13) & 0x3) << 6;
                break;
        }
    }

    // Restore the PM register
    PLX_PCI_REG_WRITE(
        pdx,
        PCI9030_PM_CSR,
        RegisterSave
        );

    if (offset == PCI9030_PM_DATA_SELECT)
    {
        return RegisterDataSelect;
    }

    if (offset == PCI9030_PM_DATA_SCALE)
    {
        return RegisterDataScale;
    }

    return (U32)-1;
}