📄 plxchip.c
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/*******************************************************************************
* Copyright (c) 2006 PLX Technology, Inc.
*
* PLX Technology Inc. licenses this software under specific terms and
* conditions. Use of any of the software or derviatives thereof in any
* product without a PLX Technology chip is strictly prohibited.
*
* PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY,
* EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee
* or representations regarding the use of, or the results of the use of,
* the software and documentation in terms of correctness, accuracy,
* reliability, currentness, or otherwise; and you rely on the software,
* documentation and results solely at your own risk.
*
* IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
* LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
* OF ANY KIND. IN NO EVENT SHALL PLX'S TOTAL LIABILITY EXCEED THE SUM
* PAID TO PLX FOR THE PRODUCT LICENSED HEREUNDER.
*
******************************************************************************/
/******************************************************************************
*
* File Name:
*
* PlxChip.c
*
* Description:
*
* This file contains functions specific to a PLX Chip.
*
* Revision History:
*
* 02-01-06 : PCI SDK v4.40
*
******************************************************************************/
#include "DriverDefs.h"
#include "PciSupport.h"
#include "PlxInterrupt.h"
#include "SupportFunc.h"
/******************************************************************************
*
* Function : PlxChipPciInterruptEnable
*
* Description: Enables the PLX Chip PCI Interrupt
*
*****************************************************************************/
BOOLEAN
PlxChipPciInterruptEnable(
DEVICE_EXTENSION *pdx
)
{
U32 RegInterrupt;
RegInterrupt =
PLX_REG_READ(
pdx,
PCI9030_INT_CTRL_STAT
);
PLX_REG_WRITE(
pdx,
PCI9030_INT_CTRL_STAT,
RegInterrupt | (1 << 6)
);
return TRUE;
}
/******************************************************************************
*
* Function : PlxChipPciInterruptDisable
*
* Description: Disables the PLX Chip PCI Interrupt
*
*****************************************************************************/
BOOLEAN
PlxChipPciInterruptDisable(
DEVICE_EXTENSION *pdx
)
{
U32 RegInterrupt;
RegInterrupt =
PLX_REG_READ(
pdx,
PCI9030_INT_CTRL_STAT
);
PLX_REG_WRITE(
pdx,
PCI9030_INT_CTRL_STAT,
RegInterrupt & ~(1 << 6)
);
return TRUE;
}
/******************************************************************************
*
* Function : PlxPciBoardReset
*
* Description: Resets a device using software reset feature of PLX chip
*
******************************************************************************/
VOID
PlxPciBoardReset(
DEVICE_EXTENSION *pdx
)
{
U8 EepromPresent;
U32 RegValue;
U32 RegInterrupt;
U32 RegHotSwap;
U32 RegPowerMgmnt;
U32 RegIntCtrlStatus;
// Added to avoid compiler warnings
RegIntCtrlStatus = 0;
// Clear any PCI errors
PLX_PCI_REG_READ(
pdx,
CFG_COMMAND,
&RegValue
);
if (RegValue & (0xf8 << 24))
{
// Write value back to clear aborts
PLX_PCI_REG_WRITE(
pdx,
CFG_COMMAND,
RegValue
);
}
// Determine if an EEPROM is present
RegValue =
PLX_REG_READ(
pdx,
PCI9030_EEPROM_CTRL
);
// Make sure S/W Reset & EEPROM reload bits are clear
RegValue &= ~((1 << 30) | (1 << 29));
// Remember if EEPROM is present
EepromPresent = (U8)((RegValue >> 28) & (1 << 0));
// Save interrupt line
PLX_PCI_REG_READ(
pdx,
CFG_INT_LINE,
&RegInterrupt
);
// Save some registers if EEPROM present
if (EepromPresent)
{
RegIntCtrlStatus =
PLX_REG_READ(
pdx,
PCI9030_INT_CTRL_STAT
);
PLX_PCI_REG_READ(
pdx,
PCI9030_HS_CAP_ID,
&RegHotSwap
);
PLX_PCI_REG_READ(
pdx,
PCI9030_PM_CSR,
&RegPowerMgmnt
);
}
// Issue Software Reset to hold PLX chip in reset
PLX_REG_WRITE(
pdx,
PCI9030_EEPROM_CTRL,
RegValue | (1 << 30)
);
// Delay for a bit
Plx_sleep(100);
// Bring chip out of reset
PLX_REG_WRITE(
pdx,
PCI9030_EEPROM_CTRL,
RegValue
);
// Issue EEPROM reload in case now programmed
PLX_REG_WRITE(
pdx,
PCI9030_EEPROM_CTRL,
RegValue | (1 << 29)
);
// Delay for a bit
Plx_sleep(10);
// Clear EEPROM reload
PLX_REG_WRITE(
pdx,
PCI9030_EEPROM_CTRL,
RegValue
);
// Restore interrupt line
PLX_PCI_REG_WRITE(
pdx,
CFG_INT_LINE,
RegInterrupt
);
// If EEPROM was present, restore registers
if (EepromPresent)
{
// Mask interrupt clear bits
RegIntCtrlStatus &= ~((1 << 11) | (1 << 10));
PLX_REG_WRITE(
pdx,
PCI9030_INT_CTRL_STAT,
RegIntCtrlStatus
);
// Mask out HS bits that can be cleared
RegHotSwap &= ~((1 << 23) | (1 << 22) | (1 << 17));
PLX_PCI_REG_WRITE(
pdx,
PCI9030_HS_CAP_ID,
RegHotSwap
);
// Mask out PM bits that can be cleared
RegPowerMgmnt &= ~(1 << 15);
PLX_PCI_REG_READ(
pdx,
PCI9030_PM_CSR,
&RegPowerMgmnt
);
}
}
/******************************************************************************
*
* Function : PlxChipSetInterruptNotifyFlags
*
* Description: Sets the interrupt notification flags of a wait object
*
******************************************************************************/
VOID
PlxChipSetInterruptNotifyFlags(
PLX_INTR *pPlxIntr,
PLX_WAIT_OBJECT *pWaitObject
)
{
// Clear notify events
pWaitObject->NotifyOnInterrupt = INTR_TYPE_NONE;
if (pPlxIntr->IopToPciInt)
pWaitObject->NotifyOnInterrupt |= INTR_TYPE_LOCAL_1;
if (pPlxIntr->IopToPciInt_2)
pWaitObject->NotifyOnInterrupt |= INTR_TYPE_LOCAL_2;
if (pPlxIntr->SwInterrupt)
pWaitObject->NotifyOnInterrupt |= INTR_TYPE_SOFTWARE;
}
/******************************************************************************
*
* Function : PlxChipGetSpace
*
* Description: Returns the BAR index and remap register offset for a space
*
******************************************************************************/
VOID
PlxChipGetSpace(
DEVICE_EXTENSION *pdx,
IOP_SPACE IopSpace,
U8 *pBarIndex,
U16 *pOffset_RegRemap
)
{
switch (IopSpace)
{
case IopSpace0:
*pBarIndex = 2;
*pOffset_RegRemap = PCI9030_REMAP_SPACE0;
break;
case IopSpace1:
*pBarIndex = 3;
*pOffset_RegRemap = PCI9030_REMAP_SPACE1;
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