s3c2410-uda1341.c

这是一个适用于三星公司S3C2410的音频驱动程序

/*
 * Philips UDA1341 Audio Device Driver for S3C2410 Linux
 *
 * Copyright (C) 2002 MIZI Research, Inc.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/poll.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/sound.h>
#include <linux/soundcard.h>

#include <linux/pm.h>

#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/semaphore.h>
#include <asm/dma.h>

#include <asm/arch/regs-gpio.h>
#include <asm/arch-s3c2410/regs-iis.h>
#include <asm/arch/regs-clock.h>
#include <linux/dma-mapping.h>

#undef  DEBUG
#ifdef DEBUG
#define DPRINTK( x... )  printk( ##x )
#else
#define DPRINTK( x... )
#endif

static void init_s3c2410_iis_bus_rx(void);
static void init_s3c2410_iis_bus_tx(void);

#define DEF_VOLUME     65

/* UDA1341 Register bits */
#define UDA1341_ADDR		0x14

#define UDA1341_REG_DATA0	(UDA1341_ADDR + 0)
#define UDA1341_REG_STATUS	(UDA1341_ADDR + 2)

/* status control */
#define STAT0			(0x00)
#define STAT0_RST               (1 << 6)
#define STAT0_SC_MASK           (3 << 4)
#define STAT0_SC_512FS          (0 << 4)
#define STAT0_SC_384FS          (1 << 4)
#define STAT0_SC_256FS          (2 << 4)
#define STAT0_IF_MASK           (7 << 1)
#define STAT0_IF_I2S            (0 << 1)
#define STAT0_IF_LSB16          (1 << 1)
#define STAT0_IF_LSB18          (2 << 1)
#define STAT0_IF_LSB20          (3 << 1)
#define STAT0_IF_MSB            (4 << 1)
#define STAT0_IF_LSB16MSB       (5 << 1)
#define STAT0_IF_LSB18MSB       (6 << 1)
#define STAT0_IF_LSB20MSB       (7 << 1)
#define STAT0_DC_FILTER         (1 << 0)
#define STAT0_DC_NO_FILTER	(0 << 0)

#define STAT1			(0x80)
#define STAT1_DAC_GAIN          (1 << 6)        /* gain of DAC */
#define STAT1_ADC_GAIN          (1 << 5)        /* gain of ADC */
#define STAT1_ADC_POL           (1 << 4)        /* polarity of ADC */
#define STAT1_DAC_POL           (1 << 3)        /* polarity of DAC */
#define STAT1_DBL_SPD           (1 << 2)        /* double speed playback */
#define STAT1_ADC_ON            (1 << 1)        /* ADC powered */
#define STAT1_DAC_ON            (1 << 0)        /* DAC powered */

/* data0 direct control */
#define DATA0     		(0x00)
#define DATA0_VOLUME_MASK       (0x3f)
#define DATA0_VOLUME(x)         (x)

#define DATA1     		(0x40)
#define DATA1_BASS(x)           ((x) << 2)
#define DATA1_BASS_MASK         (15 << 2)
#define DATA1_TREBLE(x)         ((x))
#define DATA1_TREBLE_MASK       (3)

#define DATA2     		(0x80)
#define DATA2_PEAKAFTER         (0x1 << 5)
#define DATA2_DEEMP_NONE        (0x0 << 3)
#define DATA2_DEEMP_32KHz       (0x1 << 3)
#define DATA2_DEEMP_44KHz       (0x2 << 3)
#define DATA2_DEEMP_48KHz       (0x3 << 3)
#define DATA2_MUTE              (0x1 << 2)
#define DATA2_FILTER_FLAT       (0x0 << 0)
#define DATA2_FILTER_MIN        (0x1 << 0)
#define DATA2_FILTER_MAX        (0x3 << 0)
/* data0 extend control */
#define EXTADDR(n)              (0xc0 | (n))
#define EXTDATA(d)              (0xe0 | (d))

#define EXT0                    0
#define EXT0_CH1_GAIN(x)        (x)
#define EXT1                    1
#define EXT1_CH2_GAIN(x)        (x)
#define EXT2                    2
#define EXT2_MIC_GAIN_MASK      (7 << 2)
#define EXT2_MIC_GAIN(x)        ((x) << 2)
#define EXT2_MIXMODE_DOUBLEDIFF (0)
#define EXT2_MIXMODE_CH1        (1)
#define EXT2_MIXMODE_CH2        (2)
#define EXT2_MIXMODE_MIX        (3)
#define EXT4                    4
#define EXT4_AGC_ENABLE         (1 << 4)
#define EXT4_INPUT_GAIN_MASK    (3)
#define EXT4_INPUT_GAIN(x)      ((x) & 3)
#define EXT5                    5
#define EXT5_INPUT_GAIN(x)      ((x) >> 2)
#define EXT6                    6
#define EXT6_AGC_CONSTANT_MASK  (7 << 2)
#define EXT6_AGC_CONSTANT(x)    ((x) << 2)
#define EXT6_AGC_LEVEL_MASK     (3)
#define EXT6_AGC_LEVEL(x)       (x)

#define AUDIO_NAME		"UDA1341"
#define AUDIO_NAME_VERBOSE	"UDA1341 audio driver"

#define AUDIO_FMT_MASK          (AFMT_S16_LE)
#define AUDIO_FMT_DEFAULT       (AFMT_S16_LE)

#define AUDIO_CHANNELS_DEFAULT	2
#define AUDIO_RATE_DEFAULT	22050

#define AUDIO_NBFRAGS_DEFAULT	8
#define AUDIO_FRAGSIZE_DEFAULT	8192

#define S_CLOCK_FREQ	384
#define PCM_ABS(a) (a < 0 ? -a : a)

typedef struct {
	int size;
	char *start;
	dma_addr_t dma_addr;
	struct semaphore sem;
	int master;
} audio_buf_t;

typedef struct {
	audio_buf_t *buffers;
	audio_buf_t *buf;
	u_int buf_idx;
	u_int fragsize;
	u_int nbfrags;
	dmach_t dma_ch;      
} audio_stream_t;

static audio_stream_t output_stream;
static audio_stream_t input_stream; /* input */

#define NEXT_BUF(_s_,_b_) { \
        (_s_)->_b_##_idx++; \
        (_s_)->_b_##_idx %= (_s_)->nbfrags; \
        (_s_)->_b_ = (_s_)->buffers + (_s_)->_b_##_idx; }


static u_int audio_rate;
static int audio_channels;
static int audio_fmt;
static u_int audio_fragsize;
static u_int audio_nbfrags;


static int audio_rd_refcount;
static int audio_wr_refcount;
#define audio_active		(audio_rd_refcount | audio_wr_refcount)

static int audio_dev_dsp;
static int audio_dev_mixer;
static int audio_mix_modcnt;

static int uda1341_volume;
static u8 uda_sampling;
static int uda1341_boost;
static int mixer_igain=0x4; /* -6db*/

/*
 * For the dma chanel user
 */
static struct s3c2410_dma_client s3c2410_dma_client_out ={
	.name ="I2SSDO",
};
static struct s3c2410_dma_client s3c2410_dma_client_in={
	.name ="I2SSDI",
};

#define FIN_NEW	12000000
#define GET_PCLK_NEW	0
#define DMA_CH1		1
#define DMA_CH2		2

#ifndef __ASSEMBLY__
#define UData(Data)	((unsigned long) (Data))
#else
#define UData(Data)	(Data)
#endif

#define FInsrt(Value, Field) \
	                	(UData (Value) << FShft (Field))

#define fIISPSR_A       Fld(5, 5)       /* Prescaler Control A */
#define IISPSR_A(x)     FInsrt((x), fIISPSR_A)
#define fIISPSR_B       Fld(5, 0)       /* Prescaler Control B */
#define IISPSR_B(x)     FInsrt((x), fIISPSR_B)  

#define fPLL_MDIV               Fld(8,12)
#define fPLL_PDIV               Fld(6,4)
#define fPLL_SDIV               Fld(2,0)
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
#define FShft(Field)    ((Field) & 0x0000FFFF)
#define FAlnMsk(Field)  ((UData (1) << FSize (Field)) - 1)
#define FSize(Field)    ((Field) >> 16)
#define FExtr(Data, Field) ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#define GET_MDIV(x)     FExtr(x, fPLL_MDIV)
#define GET_PDIV(x)     FExtr(x, fPLL_PDIV)
#define GET_SDIV(x)     FExtr(x, fPLL_SDIV)

/* Functions for the callback when dma transfered done */
static void audio_dmaout_done_callback(s3c2410_dma_chan_t  *r_value,void *buf_id, int size,s3c2410_dma_buffresult_t result);
static void audio_dmain_done_callback(s3c2410_dma_chan_t  *r_value,void *buf_id, int size,s3c2410_dma_buffresult_t result);


/*
 * To enble Full-Duplex
 */
static void init_s3c2410_iis_bus_txrx(void)
{
	unsigned long tmp_read;
	__raw_writel(0,S3C2410_SBC_IISCON);
	__raw_writel(0,S3C2410_SBC_IISMOD);
	__raw_writel(0,S3C2410_SBC_IISFCON);
	
	/* 8 kHZ, 384fs */
	__raw_writel((IISPSR_A(iispsr_value(S_CLOCK_FREQ, 8000)) 
	           | IISPSR_B(iispsr_value(S_CLOCK_FREQ, 8000)))
		   ,S3C2410_SBC_IISPSR);
	
	__raw_writel(S3C2410_IISCON_RXDMAEN 		 /* (1 << 4):Receive DMA service request */
		   | S3C2410_IISCON_TXDMAEN	         /* (1 << 5):Transmit DMA service request */	
		   | (1<<1)				 /* (1 << 1):IIS Prescaler Enable */
		   ,S3C2410_SBC_IISCON);
	
 	__raw_writel((0<<8) 				/* (0 << 8):Master mode */
		   | S3C2410_IISMOD_RXMODE		/* (1 << 6):Receive mode */
		   |  S3C2410_IISMOD_TXMODE		/* (2 << 6):Transmit mode */
		   | S3C2410_IISMOD_LR_LLOW		/* (0 << 5):Low for left channel */
		   | S3C2410_IISMOD_MSB			/* (1 << 4):MSB-justified format */
		   | S3C2410_IISMOD_16BIT		/* (1 << 3):Serial data bit/channel is 16 bit */
		   | (1<<2)				/* (1 << 2):Master clock freq = 384 fs */
		   | S3C2410_IISMOD_32FS		/* (1 << 0):32 fs */
		   ,S3C2410_SBC_IISMOD);
	
 	__raw_writel(S3C2410_IISFCON_TXDMA		/* (1 << 15):Transmit FIFO access mode:DMA */
		   | S3C2410_IISFCON_RXDMA		/* (1 << 14):Receive FIFO access mode:DMA */
		   | S3C2410_IISFCON_TXENABLE		/* (1 << 13):Transmit FIFO enable */
		   | S3C2410_IISFCON_RXENABLE		/* (1 << 12):Receive FIFO access enable */
		   ,S3C2410_SBC_IISFCON);
	
	tmp_read=__raw_readl(S3C2410_SBC_IISCON);
	tmp_read=tmp_read | S3C2410_IISCON_IISEN;	/* IIS enable(start) */
	__raw_writel(tmp_read,S3C2410_SBC_IISCON);
}

static void uda1341_l3_address(u8 data)
{
	int i;
	unsigned long flags;

	local_irq_save(flags);
	/*
	 * To set Bit 2 of GPBDAT Register (physical address:0x56000014)
	 * to be 0
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,0);
	/*
	 * To set Bit 3 of GPBDAT Register (physical address:0x56000014)
	 * to be 0
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB3,0);
	/*
	 * To set Bit 4 of GPBDAT Register (physical address:0x56000014)
	 * to 0
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB4,1);
	udelay(1);
	
	for (i = 0; i < 8; i++) {
		if (data & 0x1) {
			/*
			 * To set Bit 4 of GPBDAT to be 0(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,0);
			udelay(1);
			/*
			 * To set Bit 3 of GPBDAT to be 1(GPIO_L3DATA=0x01010103)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB3,1);
			udelay(1);
			/*
			 * To set Bit 4 of GPBDAT to be 1(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,1);
			udelay(1);
		} else {
			/*
			 * To set Bit 4 of GPBDAT to be 0(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,0);
			udelay(1);
			/*
			 * To set Bit 3 of GPBDAT to be 0(/GPIO_L3DATA=0x01010103)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB3,0);
			udelay(1);
			/*
			 * To set Bit 4 of GPBDAT to be 1(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,1);
			udelay(1);
		}
		data >>= 1;
	}

	/*
	 * To set Bit 2 of GPBDAT to be 1(GPIO_L3MODE=0x01010102)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,1);
	udelay(1);
	local_irq_restore(flags);
}


/* To input the data */ 
static void uda1341_l3_data(u8 data)
{
	int i;
	unsigned long flags;

	local_irq_save(flags);

	/*
	 * To set Bit 2 of GPBDAT to be 1(GPIO_L3MODE=0x0101010)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,1);
	udelay(1);
	/*
	 * To set Bit 2 of GPBDAT to be 0(GPIO_L3MODE=0x01010102)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,0);
	udelay(1);
	/*
	 * To set Bit 2 of GPBDAT to be 1(GPIO_L3MODE=0x01010102)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,1);
	for (i = 0; i < 8; i++) {
		if (data & 0x1) {
			/*
			 * To set Bit 4 of GPBDAT to be 0(GPIO_L3CLOCK=0x01010104)
			 */
			s3c2410_gpio_setpin(S3C2410_GPB4,0);
			udelay(1);
			/*
			 * To set Bit 3 of GPBDAT to be 1(GPIO_L3DATA=0x01010103)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB3,1);
			udelay(1);
			/*
			 * To set Bit 4 of GPBDAT to be 1(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,1);
			udelay(1);
		} else {
			/*
			 * To set Bit 4 of GPBDAT to be 0(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,0);
			udelay(1);
			/*
			 * To set Bit 3 of GPBDAT to be 0(GPIO_L3DATA=0x01010103)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB3,0);
			udelay(1);
			/*
			 * To set Bit 4 of GPBDAT to be 1(GPIO_L3CLOCK=0x01010104)
			 */ 
			s3c2410_gpio_setpin(S3C2410_GPB4,1);
			udelay(1);
		}

		data >>= 1;
	}

	/*
	 * To set Bit 2 of GPBDAT to be 1(GPIO_L3MODE=0x01010102)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,1);
	/*
	 * To set Bit 2 of GPBDAT to be 0(GPIO_L3MODE=0x01010102)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,0);
	udelay(1);
	/*
	 * To set Bit 2 of GPBDAT to be 1(GPIO_L3MODE=0x01010102)
	 */ 
	s3c2410_gpio_setpin(S3C2410_GPB2,1);
	local_irq_restore(flags);
}

static void audio_clear_buf(audio_stream_t * s)
{
    	DPRINTK("audio_clear_buf\n");

	s3c2410_dma_ctrl(s->dma_ch, S3C2410_DMAOP_FLUSH);
	if (s->buffers) {
		int frag;

		for (frag = 0; frag < s->nbfrags; frag++) {
			if (!s->buffers[frag].master)
				continue;
			/* To free the dma buffer */ 
			dma_free_coherent(NULL,s->buffers[frag].master,s->buffers[frag].start ,s->buffers[frag].dma_addr);
		}
		kfree(s->buffers);
		s->buffers = NULL;
	}

	s->buf_idx = 0;
	s->buf = NULL;
}

static int audio_setup_buf(audio_stream_t * s)
{
	int frag;
	int dmasize = 0;
	char *dmabuf = 0;
	dma_addr_t dmaphys = 0;

	if (s->buffers)
	{
		return -EBUSY;
	}

	s->nbfrags = audio_nbfrags;
	s->fragsize = audio_fragsize;

	s->buffers = (audio_buf_t *)
	    kmalloc(sizeof(audio_buf_t) * s->nbfrags, GFP_KERNEL);
	if (!s->buffers)
		goto err;
	memset(s->buffers, 0, sizeof(audio_buf_t) * s->nbfrags);

	for (frag = 0; frag < s->nbfrags; frag++) {
		audio_buf_t *b = &s->buffers[frag];

		if (!dmasize) {
			dmasize = (s->nbfrags - frag) * s->fragsize;
			do {
				/*
				 * To allocate the coherent address buffer for dma transfer
				 */ 
				dmabuf=dma_alloc_coherent(NULL,dmasize,&dmaphys,GFP_KERNEL|GFP_DMA);  
				if (!dmabuf) 
				    	dmasize -= s->fragsize;
			} while (!dmabuf && dmasize);
			if (!dmabuf)
				goto err;
			b->master = dmasize;
		}