cmos_fifo_usb.srr

来自「cmos数据到fifo再到usb的fifo部分程序(68013a)」· SRR 代码 · 共 27 行

#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\acter\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: PRIMAX-142F7BC7

#Implementation: synthesis

#Tue May 20 23:22:02 2008

$ Start of Compile
#Tue May 20 23:22:02 2008

Synplicity Verilog Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@I::"C:\acter\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v"
@I::"E:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v"
@I::"E:\fpga_test\cmos_fifo_usb\smartgen\usb_fifo32x16\usb_fifo32x16.v"
@I::"E:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v"
@E: CS187 :"E:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":14:37:14:37|Expecting ,
1 syntax errors
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue May 20 23:22:02 2008

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