stdout.log

来自「cmos数据到fifo再到usb的fifo部分程序(68013a)」· LOG 代码 · 共 40 行

Starting:    C:\Libero\Synplify\Synplify_88A1\bin\mbin\synplify.exe
Install:     C:\Libero\Synplify\Synplify_88A1
Date:        Wed May 21 14:37:47 2008
Version:     8.8A1


Arguments:   cmos_fifo_usb_syn.prj
ProductType: synplify

License checkout: synplify_pc
License: synplify_pc node-locked 



Running synthesis on cmos_fifo_usb_syn:synthesis

log file: "H:\fpga_test\cmos_fifo_usb\synthesis\cmos_fifo_usb.srr"


Running Verilog Compiler...

Verilog Compiler Completed


Total: 0 errors, 28 warnings, 10 notes


Running ProASIC3 Mapper...

ProASIC3 Mapper Completed


Total: 0 errors, 28 warnings, 17 notes


exit status=0