cmos_fifo_usb.sdf

cmos数据到fifo再到usb的fifo部分程序(68013a)

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  waddr_n10_0_m6_i_o2_3/A  waddr_n10_0_m6_i_o2_3/Y  waddr_n10_0_m6_i_o2/B  waddr_n10_0_m6_i_o2/Y  waddr_n10_0_m6_i/B  waddr_n10_0_m6_i/Y  waddr\[10\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  ren_6_i_a2_8/B  ren_6_i_a2_8/Y  ren_6_i_a2_10/C  ren_6_i_a2_10/Y  ren_6_i_a2/C  ren_6_i_a2/Y  ren/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT ren/CLK  ren/Q  raddr_0_sqmuxa_0_a2_s/B  raddr_0_sqmuxa_0_a2_s/Y  raddr_n1_i_1_2/B  raddr_n1_i_1_2/Y  raddr_n1_i_1/C  raddr_n1_i_1/Y  raddr\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[3\]/CLK  waddr\[3\]/Q  waddr_n10_0_m6_i_o2_3/C  waddr_n10_0_m6_i_o2_3/Y  waddr_n10_0_m6_i_o2/B  waddr_n10_0_m6_i_o2/Y  waddr_n10_0_m6_i/B  waddr_n10_0_m6_i/Y  waddr\[10\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[7\]/CLK  waddr\[7\]/Q  waddr_n10_0_m6_i_o2_3/B  waddr_n10_0_m6_i_o2_3/Y  waddr_n10_0_m6_i_o2/B  waddr_n10_0_m6_i_o2/Y  waddr_n10_0_m6_i/B  waddr_n10_0_m6_i/Y  waddr\[10\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  waddr_n2_i_o2/A  waddr_n2_i_o2/Y  waddr_n10_0_m6_i_o2/C  waddr_n10_0_m6_i_o2/Y  waddr_n10_0_m6_i/B  waddr_n10_0_m6_i/Y  waddr\[10\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[8\]/CLK  raddr\[8\]/Q  raddr_n1_i_1_0/A  raddr_n1_i_1_0/Y  raddr_n1_i_1_2/A  raddr_n1_i_1_2/Y  raddr_n1_i_1/C  raddr_n1_i_1/Y  raddr\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[5\]/CLK  waddr\[5\]/Q  waddr_n9_0_a0_5/A  waddr_n9_0_a0_5/Y  waddr_n9_0_a0/A  waddr_n9_0_a0/Y  waddr_n9/A  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  waddr_n9_0_a0_4/A  waddr_n9_0_a0_4/Y  waddr_n9_0_a0/B  waddr_n9_0_a0/Y  waddr_n9/A  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  u1/OR2A_ENABLE_ADDRB_1_inst/B  u1/OR2A_ENABLE_ADDRB_1_inst/Y  u1/ORB_GATE_1_inst/A  u1/ORB_GATE_1_inst/Y  u1/two_port1280x8_R1C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[4\]/CLK  waddr\[4\]/Q  waddr_n10_0_m6_i_o2_4/B  waddr_n10_0_m6_i_o2_4/Y  waddr_n10_0_m6_i_o2/A  waddr_n10_0_m6_i_o2/Y  waddr_n10_0_m6_i/B  waddr_n10_0_m6_i/Y  waddr\[10\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[1\]/CLK  waddr\[1\]/Q  waddr_n2_i_o2/B  waddr_n2_i_o2/Y  waddr_n10_0_m6_i_o2/C  waddr_n10_0_m6_i_o2/Y  waddr_n10_0_m6_i/B  waddr_n10_0_m6_i/Y  waddr\[10\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[6\]/CLK  raddr\[6\]/Q  raddr_n7_i_o3_s/B  raddr_n7_i_o3_s/Y  raddr_n8_i_o3/A  raddr_n8_i_o3/Y  raddr_n8_i/B  raddr_n8_i/Y  raddr\[8\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[6\]/CLK  raddr\[6\]/Q  raddr_n7_i_o3_s/B  raddr_n7_i_o3_s/Y  raddr_n8_i_a3/B  raddr_n8_i_a3/Y  raddr_n8_i/A  raddr_n8_i/Y  raddr\[8\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[7\]/CLK  waddr\[7\]/Q  waddr_n9_0_a0_4/B  waddr_n9_0_a0_4/Y  waddr_n9_0_a0/B  waddr_n9_0_a0/Y  waddr_n9/A  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  u1/OR2A_ENABLE_ADDRB_2_inst/A  u1/OR2A_ENABLE_ADDRB_2_inst/Y  u1/ORB_GATE_2_inst/A  u1/ORB_GATE_2_inst/Y  u1/two_port1280x8_R2C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  u1/OR2_ENABLE_ADDRB_0_inst/A  u1/OR2_ENABLE_ADDRB_0_inst/Y  u1/ORB_GATE_0_inst/A  u1/ORB_GATE_0_inst/Y  u1/two_port1280x8_R0C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[7\]/CLK  raddr\[7\]/Q  raddr_n7_i_o3_s/A  raddr_n7_i_o3_s/Y  raddr_n8_i_o3/A  raddr_n8_i_o3/Y  raddr_n8_i/B  raddr_n8_i/Y  raddr\[8\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[4\]/CLK  waddr\[4\]/Q  waddr_n9_0_a0_5/B  waddr_n9_0_a0_5/Y  waddr_n9_0_a0/A  waddr_n9_0_a0/Y  waddr_n9/A  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[8\]/CLK  waddr\[8\]/Q  ren_6_i_a2_8/C  ren_6_i_a2_8/Y  ren_6_i_a2_10/C  ren_6_i_a2_10/Y  ren_6_i_a2/C  ren_6_i_a2/Y  ren/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[1\]/CLK  waddr\[1\]/Q  ren_6_i_a2_5/B  ren_6_i_a2_5/Y  ren_6_i_a2_10/B  ren_6_i_a2_10/Y  ren_6_i_a2/C  ren_6_i_a2/Y  ren/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[5\]/CLK  waddr\[5\]/Q  waddr_n6_i_a2/B  waddr_n6_i_a2/Y  waddr_n6_i/C  waddr_n6_i/Y  waddr\[6\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  ren_6_i_a2_5/A  ren_6_i_a2_5/Y  ren_6_i_a2_10/B  ren_6_i_a2_10/Y  ren_6_i_a2/C  ren_6_i_a2/Y  ren/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[8\]/CLK  raddr\[8\]/Q  u1/OR2_ENABLE_ADDRB_0_inst/B  u1/OR2_ENABLE_ADDRB_0_inst/Y  u1/ORB_GATE_0_inst/A  u1/ORB_GATE_0_inst/Y  u1/two_port1280x8_R0C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[8\]/CLK  raddr\[8\]/Q  u1/OR2A_ENABLE_ADDRB_2_inst/B  u1/OR2A_ENABLE_ADDRB_2_inst/Y  u1/ORB_GATE_2_inst/A  u1/ORB_GATE_2_inst/Y  u1/two_port1280x8_R2C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  raddr_n1_i_a0_0/A  raddr_n1_i_a0_0/Y  raddr_n1_i_1/B  raddr_n1_i_1/Y  raddr\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[2\]/CLK  waddr\[2\]/Q  waddr_n2_i_o2/C  waddr_n2_i_o2/Y  waddr_n3_i/A  waddr_n3_i/Y  waddr\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[8\]/CLK  raddr\[8\]/Q  u1/OR2A_ENABLE_ADDRB_1_inst/A  u1/OR2A_ENABLE_ADDRB_1_inst/Y  u1/ORB_GATE_1_inst/A  u1/ORB_GATE_1_inst/Y  u1/two_port1280x8_R1C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[0\]/CLK  raddr\[0\]/Q  raddr_n1_i_o3/B  raddr_n1_i_o3/Y  raddr_n2_i/A  raddr_n2_i/Y  raddr\[2\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[9\]/CLK  waddr\[9\]/Q  ren_6_i_a2_7/A  ren_6_i_a2_7/Y  ren_6_i_a2_10/A  ren_6_i_a2_10/Y  ren_6_i_a2/C  ren_6_i_a2/Y  ren/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[9\]/CLK  waddr\[9\]/Q  u1/OR2A_ENABLE_ADDRA_2_inst/B  u1/OR2A_ENABLE_ADDRA_2_inst/Y  u1/ORA_GATE_2_inst/A  u1/ORA_GATE_2_inst/Y  u1/two_port1280x8_R2C0/WEN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[9\]/CLK  waddr\[9\]/Q  u1/OR2_ENABLE_ADDRA_0_inst/B  u1/OR2_ENABLE_ADDRA_0_inst/Y  u1/ORA_GATE_0_inst/A  u1/ORA_GATE_0_inst/Y  u1/two_port1280x8_R0C0/WEN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[9\]/CLK  waddr\[9\]/Q  u1/OR2A_ENABLE_ADDRA_1_inst/A  u1/OR2A_ENABLE_ADDRA_1_inst/Y  u1/ORA_GATE_1_inst/A  u1/ORA_GATE_1_inst/Y  u1/two_port1280x8_R1C0/WEN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  raddr_n9_0_a3_0_0/C  raddr_n9_0_a3_0_0/Y  raddr_n9_0/B  raddr_n9_0/Y  raddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[8\]/CLK  raddr\[8\]/Q  raddr_n8_i_o3/B  raddr_n8_i_o3/Y  raddr_n8_i/B  raddr_n8_i/Y  raddr\[8\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  waddr_n6_i_a2/C  waddr_n6_i_a2/Y  waddr_n6_i/C  waddr_n6_i/Y  waddr\[6\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  raddr_n9_0_a3_1/B  raddr_n9_0_a3_1/Y  raddr_n9_0/C  raddr_n9_0/Y  raddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_count\[0\]/CLK  head_count\[0\]/Q  head_count_n1_i_o2_0/B  head_count_n1_i_o2_0/Y  head_count_n2_i_o2/B  head_count_n2_i_o2/Y  head_count_n3_i/A  head_count_n3_i/Y  head_count\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[10\]/CLK  waddr\[10\]/Q  u1/OR2A_ENABLE_ADDRA_1_inst/B  u1/OR2A_ENABLE_ADDRA_1_inst/Y  u1/ORA_GATE_1_inst/A  u1/ORA_GATE_1_inst/Y  u1/two_port1280x8_R1C0/WEN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[2\]/CLK  waddr\[2\]/Q  waddr_n9_0/A  waddr_n9_0/Y  waddr_n9/B  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[10\]/CLK  waddr\[10\]/Q  u1/OR2A_ENABLE_ADDRA_2_inst/A  u1/OR2A_ENABLE_ADDRA_2_inst/Y  u1/ORA_GATE_2_inst/A  u1/ORA_GATE_2_inst/Y  u1/two_port1280x8_R2C0/WEN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[7\]/CLK  waddr\[7\]/Q  waddr_n7_i_a2/A  waddr_n7_i_a2/Y  waddr_n7_i/B  waddr_n7_i/Y  waddr\[7\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[10\]/CLK  waddr\[10\]/Q  u1/OR2_ENABLE_ADDRA_0_inst/A  u1/OR2_ENABLE_ADDRA_0_inst/Y  u1/ORA_GATE_0_inst/A  u1/ORA_GATE_0_inst/Y  u1/two_port1280x8_R0C0/WEN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[4\]/CLK  waddr\[4\]/Q  waddr_n4_i_a2/C  waddr_n4_i_a2/Y  waddr_n4_i/A  waddr_n4_i/Y  waddr\[4\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_count\[1\]/CLK  head_count\[1\]/Q  head_count_n1_i_o2_0/A  head_count_n1_i_o2_0/Y  head_count_n2_i_o2/B  head_count_n2_i_o2/Y  head_count_n3_i/A  head_count_n3_i/Y  head_count\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[9\]/CLK  waddr\[9\]/Q  waddr_n9_0/B  waddr_n9_0/Y  waddr_n9/B  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_en/CLK  head_en/Q  head_count_n1_i_o2/B  head_count_n1_i_o2/Y  head_count_n0_0_a2/B  head_count_n0_0_a2/Y  head_count\[0\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[6\]/CLK  raddr\[6\]/Q  raddr_n7_i_0/A  raddr_n7_i_0/Y  raddr_n7_i/A  raddr_n7_i/Y  raddr\[7\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[8\]/CLK  raddr\[8\]/Q  raddr_n8_i_a3/C  raddr_n8_i_a3/Y  raddr_n8_i/A  raddr_n8_i/Y  raddr\[8\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[2\]/CLK  raddr\[2\]/Q  raddr_n3_i_a3/B  raddr_n3_i_a3/Y  raddr_n3_i/A  raddr_n3_i/Y  raddr\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[4\]/CLK  raddr\[4\]/Q  raddr_n5_i_a3/B  raddr_n5_i_a3/Y  raddr_n5_i/A  raddr_n5_i/Y  raddr\[5\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[9\]/CLK  waddr\[9\]/Q  waddr_n9_0_7/C  waddr_n9_0_7/Y  waddr_n9/C  waddr_n9/Y  waddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_en/CLK  head_en/Q  head_count_n1_i_o2/B  head_count_n1_i_o2/Y  head_count_n3_i/C  head_count_n3_i/Y  head_count\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_en/CLK  head_en/Q  head_count_n1_i_o2/B  head_count_n1_i_o2/Y  head_count_n2_i/C  head_count_n2_i/Y  head_count\[2\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_en/CLK  head_en/Q  head_count_n1_i_o2/B  head_count_n1_i_o2/Y  head_count_n1_i/C  head_count_n1_i/Y  head_count\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT ren/CLK  ren/Q  u1/ORB_GATE_2_inst/B  u1/ORB_GATE_2_inst/Y  u1/two_port1280x8_R2C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT ren/CLK  ren/Q  u1/ORB_GATE_1_inst/B  u1/ORB_GATE_1_inst/Y  u1/two_port1280x8_R1C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT ren/CLK  ren/Q  u1/ORB_GATE_0_inst/B  u1/ORB_GATE_0_inst/Y  u1/two_port1280x8_R0C0/REN  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT ren/CLK  ren/Q  raddr_n9_0_a3_0_0/B  raddr_n9_0_a3_0_0/Y  raddr_n9_0/B  raddr_n9_0/Y  raddr\[9\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  raddr_n0_0_a3/A  raddr_n0_0_a3/Y  raddr\[0\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[3\]/CLK  waddr\[3\]/Q  waddr_n3_i/B  waddr_n3_i/Y  waddr\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[5\]/CLK  waddr\[5\]/Q  waddr_n5_i/B  waddr_n5_i/Y  waddr\[5\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[7\]/CLK  raddr\[7\]/Q  raddr_n7_i_0/C  raddr_n7_i_0/Y  raddr_n7_i/A  raddr_n7_i/Y  raddr\[7\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[5\]/CLK  waddr\[5\]/Q  u1/two_port1280x8_R2C0/WADDR5  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[5\]/CLK  waddr\[5\]/Q  u1/two_port1280x8_R0C0/WADDR5  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[5\]/CLK  waddr\[5\]/Q  u1/two_port1280x8_R1C0/WADDR5  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[9\]/CLK  raddr\[9\]/Q  ren_6_i_a2/B  ren_6_i_a2/Y  ren/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT head_count\[0\]/CLK  head_count\[0\]/Q  head_count_n1_i_o2_0/B  head_count_n1_i_o2_0/Y  head_count_n2_i/A  head_count_n2_i/Y  head_count\[2\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  u1/two_port1280x8_R2C0/WADDR6  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  u1/two_port1280x8_R0C0/WADDR6  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[6\]/CLK  waddr\[6\]/Q  u1/two_port1280x8_R1C0/WADDR6  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT raddr\[0\]/CLK  raddr\[0\]/Q  raddr_n0_0_a3_0/A  raddr_n0_0_a3_0/Y  raddr_n0_0_a3/C  raddr_n0_0_a3/Y  raddr\[0\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[5\]/CLK  raddr\[5\]/Q  raddr_n5_i_a3/C  raddr_n5_i_a3/Y  raddr_n5_i/A  raddr_n5_i/Y  raddr\[5\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT raddr\[3\]/CLK  raddr\[3\]/Q  raddr_n3_i_a3/C  raddr_n3_i_a3/Y  raddr_n3_i/A  raddr_n3_i/Y  raddr\[3\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[2\]/CLK  waddr\[2\]/Q  waddr_n2_i/B  waddr_n2_i/Y  waddr\[2\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT ren/CLK  ren/Q  fifoaddr_6_i\[1\]/A  fifoaddr_6_i\[1\]/Y  fifoaddr_1\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  waddr_n1_i/A  waddr_n1_i/Y  waddr\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[2\]/CLK  waddr\[2\]/Q  u1/two_port1280x8_R2C0/WADDR2  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[2\]/CLK  waddr\[2\]/Q  u1/two_port1280x8_R0C0/WADDR2  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[2\]/CLK  waddr\[2\]/Q  u1/two_port1280x8_R1C0/WADDR2  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[4\]/CLK  waddr\[4\]/Q  u1/two_port1280x8_R2C0/WADDR4  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[4\]/CLK  waddr\[4\]/Q  u1/two_port1280x8_R0C0/WADDR4  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[4\]/CLK  waddr\[4\]/Q  u1/two_port1280x8_R1C0/WADDR4  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[3\]/CLK  waddr\[3\]/Q  u1/two_port1280x8_R2C0/WADDR3  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[3\]/CLK  waddr\[3\]/Q  u1/two_port1280x8_R0C0/WADDR3  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[3\]/CLK  waddr\[3\]/Q  u1/two_port1280x8_R1C0/WADDR3  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[7\]/CLK  waddr\[7\]/Q  u1/two_port1280x8_R2C0/WADDR7  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[7\]/CLK  waddr\[7\]/Q  u1/two_port1280x8_R0C0/WADDR7  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[7\]/CLK  waddr\[7\]/Q  u1/two_port1280x8_R1C0/WADDR7  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[8\]/CLK  waddr\[8\]/Q  waddr_n8_0/A  waddr_n8_0/Y  waddr\[8\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  u1/two_port1280x8_R2C0/WADDR0  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  u1/two_port1280x8_R0C0/WADDR0  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  u1/two_port1280x8_R1C0/WADDR0  	(8.9:8.9:8.9) )

    (PATHCONSTRAINT waddr\[0\]/CLK  waddr\[0\]/Q  waddr_n0_0_a2/A  waddr_n0_0_a2/Y  waddr\[0\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT waddr\[1\]/CLK  waddr\[1\]/Q  waddr_n1_i/B  waddr_n1_i/Y  waddr\[1\]/D  	(9.7:9.7:9.7) )

    (PATHCONSTRAINT wen/CLK  wen/Q  u1/ORA_GATE_0_inst/B  u1/ORA_GATE_0_inst/Y  u1/two_port1280x8_R0C0/WEN  	(8.9:8.9:8.9) )