📄 cmos_fifo_usb.srr
字号:
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------------
cmos_fifo_usb|wclk 100.0 MHz 126.4 MHz 10.000 7.909 2.091 inferred Inferred_clkgroup_0
=========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------
cmos_fifo_usb|wclk cmos_fifo_usb|wclk | 10.000 2.091 | No paths - | No paths - | No paths -
==============================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: cmos_fifo_usb|wclk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------
waddr[0] cmos_fifo_usb|wclk DFN1C0 Q waddr[0] 0.483 2.091
waddr[1] cmos_fifo_usb|wclk DFN1C0 Q waddr[1] 0.483 2.314
waddr[2] cmos_fifo_usb|wclk DFN1C0 Q waddr[2] 0.483 2.851
waddr[4] cmos_fifo_usb|wclk DFN1C0 Q waddr[4] 0.483 2.867
waddr[3] cmos_fifo_usb|wclk DFN1C0 Q waddr[3] 0.483 2.948
ren cmos_fifo_usb|wclk DFN1P0 Q ren 0.388 3.097
raddr[0] cmos_fifo_usb|wclk DFN1C0 Q raddr[0] 0.388 3.100
raddr[2] cmos_fifo_usb|wclk DFN1C0 Q raddr[2] 0.388 3.151
raddr[4] cmos_fifo_usb|wclk DFN1C0 Q raddr[4] 0.388 3.303
raddr[5] cmos_fifo_usb|wclk DFN1C0 Q raddr[5] 0.388 3.315
=====================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
waddr[7] cmos_fifo_usb|wclk DFN1C0 D waddr_n7_i 9.590 2.091
waddr[6] cmos_fifo_usb|wclk DFN1C0 D waddr_n6_i 9.590 2.753
raddr[3] cmos_fifo_usb|wclk DFN1C0 D N_9 9.590 3.097
raddr[5] cmos_fifo_usb|wclk DFN1C0 D N_13 9.590 3.097
raddr[8] cmos_fifo_usb|wclk DFN1C0 D N_19 9.590 3.097
raddr[9] cmos_fifo_usb|wclk DFN1C0 D raddr_n9 9.590 3.100
raddr[7] cmos_fifo_usb|wclk DFN1C0 D N_17 9.590 3.168
raddr[2] cmos_fifo_usb|wclk DFN1C0 D N_7 9.590 3.281
raddr[4] cmos_fifo_usb|wclk DFN1C0 D N_11 9.590 3.281
raddr[6] cmos_fifo_usb|wclk DFN1C0 D N_15 9.590 3.281
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 7.499
= Slack (critical) : 2.091
Number of logic level(s): 5
Starting point: waddr[0] / Q
Ending point: waddr[7] / D
The start point is clocked by cmos_fifo_usb|wclk [rising] on pin CLK
The end point is clocked by cmos_fifo_usb|wclk [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------
waddr[0] DFN1C0 Q Out 0.483 0.483 -
waddr[0] Net - - 1.470 - 8
waddr_n1_i_o2 NOR2B B In - 1.953 -
waddr_n1_i_o2 NOR2B Y Out 0.466 2.419 -
N_86 Net - - 1.324 - 7
waddr_n4_i_o2 NOR2B B In - 3.743 -
waddr_n4_i_o2 NOR2B Y Out 0.466 4.209 -
N_89 Net - - 0.841 - 4
waddr_n6_i_o2 NOR2B B In - 5.050 -
waddr_n6_i_o2 NOR2B Y Out 0.466 5.516 -
N_91 Net - - 0.469 - 2
waddr_n7_i_a2 OR2 B In - 5.985 -
waddr_n7_i_a2 OR2 Y Out 0.481 6.466 -
waddr_n7_i_a2 Net - - 0.279 - 1
waddr_n7_i NOR3B B In - 6.745 -
waddr_n7_i NOR3B Y Out 0.475 7.220 -
waddr_n7_i Net - - 0.279 - 1
waddr[7] DFN1C0 D In - 7.499 -
===============================================================================
Total path delay (propagation time + setup) of 7.909 is 3.248(41.1%) logic and 4.661(58.9%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell cmos_fifo_usb.verilog
Core Cell usage:
cell count area count*area
AO1 1 1.0 1.0
AO1B 2 1.0 2.0
AO1C 1 1.0 1.0
AO1D 1 1.0 1.0
AOI1 8 1.0 8.0
AOI1B 2 1.0 2.0
AX1E 1 1.0 1.0
BUFF 10 1.0 10.0
GND 2 0.0 0.0
MX2 32 1.0 32.0
NOR2 5 1.0 5.0
NOR2A 9 1.0 9.0
NOR2B 19 1.0 19.0
NOR3 8 1.0 8.0
NOR3A 5 1.0 5.0
NOR3B 1 1.0 1.0
NOR3C 13 1.0 13.0
OA1A 1 1.0 1.0
OA1B 1 1.0 1.0
OA1C 1 1.0 1.0
OR2 11 1.0 11.0
OR2A 7 1.0 7.0
OR2B 3 1.0 3.0
OR3B 2 1.0 2.0
OR3C 2 1.0 2.0
VCC 2 0.0 0.0
XA1B 9 1.0 9.0
XA1C 2 1.0 2.0
DFN1 4 1.0 4.0
DFN1C0 37 1.0 37.0
DFN1P0 2 1.0 2.0
RAM512X18 3 0.0 0.0
----- ----------
TOTAL 207 200.0
IO Cell usage:
cell count
INBUF 14
OUTBUF 2
TRIBUFF 16
-----
TOTAL 32
Core Cells : 200 of 61536 (0%)
IO Cells : 32
RAM/ROM Usage Summary
Block Rams : 3 of 4 (75%)
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Wed May 21 14:38:01 2008
###########################################################]
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