cmos_fifo_usb.srr

cmos数据到fifo再到usb的fifo部分程序(68013a)

#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: ZHOUHUAGOU

#Implementation: synthesis

#Wed May 21 14:37:58 2008

$ Start of Compile
#Wed May 21 14:37:58 2008

Synplicity Verilog Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@I::"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v"
@I::"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v"
@I::"H:\fpga_test\cmos_fifo_usb\smartgen\usb_fifo32x16\usb_fifo32x16.v"
@I::"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v"
Verilog syntax check successful!
File H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v changed - recompiling
Selecting top level module cmos_fifo_usb
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1705:7:1705:9|Synthesizing module VCC

@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1094:7:1094:9|Synthesizing module GND

@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1238:7:1238:9|Synthesizing module MX2

@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1383:7:1383:10|Synthesizing module OR2A

@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1377:7:1377:9|Synthesizing module OR2

@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1927:8:1927:16|Synthesizing module RAM512X18

@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":854:7:854:10|Synthesizing module DFN1

@N: CG364 :"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v":5:7:5:20|Synthesizing module two_port1280x8

@W: CL168 :"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v":197:9:197:19|Pruning instance AFF1_1_inst - not in use ...

@W: CL168 :"H:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v":162:9:162:19|Pruning instance AFF1_0_inst - not in use ...

@N: CG364 :"H:\fpga_test\cmos_fifo_usb\smartgen\usb_fifo32x16\usb_fifo32x16.v":5:7:5:19|Synthesizing module usb_fifo32x16

@N: CG364 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":8:12:8:24|Synthesizing module cmos_fifo_usb

@W: CG133 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":63:20:63:29|No assignment to data_count
@W: CG133 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":74:20:74:26|No assignment to inraddr
@W: CL168 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":138:19:138:20|Pruning instance u2 - not in use ...

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":378:4:378:9|Pruning Register lighttime[15:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":378:4:378:9|Pruning Register led_control 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_6_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_2_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_7_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_3_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_8_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_4_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_0_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_9_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_5_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":367:4:367:9|Pruning Register fifodata_1_[7:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":355:4:355:9|Pruning Register fifo_count[6:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":343:4:343:9|Pruning Register inwaddr[3:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":328:4:328:9|Pruning Register inren 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":316:4:316:9|Pruning Register inwaddr[3:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":304:4:304:9|Pruning Register inwen 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":292:4:292:9|Pruning Register usbdata[15:0] 

@W: CL169 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":255:4:255:9|Pruning Register rd_out[15:0] 

@W: CL189 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":280:4:280:9|Register bit fifoaddr[0] is always 0, optimizing ...
@W: CL171 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":280:4:280:9|Pruning Register bit <0> of fifoaddr[1:0] 

@W: CL159 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":23:20:23:22|Input clk is unused
@W: CL159 :"H:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":28:20:28:24|Input empty is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 21 14:37:58 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 8.8.0, Build 015R, Built Apr 15 2007 16:31:14
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8A1
@N: MF249 |Running in 32-bit mode.


Automatic dissolve at startup in view:work.cmos_fifo_usb(verilog) of u1(two_port1280x8)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 41MB)
@N:"h:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":231:6:231:11|Found counter in view:work.cmos_fifo_usb(verilog) inst raddr[9:0]
@N:"h:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":219:4:219:9|Found counter in view:work.cmos_fifo_usb(verilog) inst waddr[10:0]
@N:"h:\fpga_test\cmos_fifo_usb\hdl\cmos_fifo.v":171:4:171:9|Found counter in view:work.cmos_fifo_usb(verilog) inst head_count[3:0]

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 41MB peak: 41MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 41MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 41MB)

Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 42MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name     Fanout, notes                 
-------------------------------------------------------------
u1.BFF2_1_inst / Q             16                            
u1.BFF2_0_inst / Q             16                            
wd_0_sqmuxa_i_o2 / Y           20                            
rd_1_i_a2 / Y                  16                            
reset_pad / Y                  42 : 39 asynchronous set/reset
=============================================================

Buffering reset_c, fanout 42 segments 4
Buffering wclk_c, fanout 49 segments 5
Replicating Combinational Instance rd_1_i_a2, fanout 16 segments 2
Replicating Combinational Instance wd_0_sqmuxa_i_o2, fanout 20 segments 2
Buffering u1.ADDRB_FF2_0_net, fanout 16 segments 2
Buffering u1.ADDRB_FF2_1_net, fanout 16 segments 2
Buffering wclk_c, fanout 13 segments 2

Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 42MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 42MB)

Added 10 Buffers
Added 2 Cells via replication
	Added 0 Sequential Cells via replication
	Added 2 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 41MB peak: 42MB)
Writing Analyst data base H:\fpga_test\cmos_fifo_usb\synthesis\cmos_fifo_usb.srm
@N: BN225 |Writing default property annotation file H:\fpga_test\cmos_fifo_usb\synthesis\cmos_fifo_usb.map.
Writing EDIF Netlist and constraint files
Found clock cmos_fifo_usb|wclk with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed May 21 14:38:01 2008
#


Top view:               cmos_fifo_usb
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.40, P = 1.33, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        PA3
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 2.091

                       Requested     Estimated     Requested     Estimated               Clock        Clock