usb_fifo32x16.gen

cmos数据到fifo再到usb的fifo部分程序(68013a)

Version:8.0.0.40
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_RAM
LPM_HINT:TWO
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
"DESDIR:H:/fpga_test/cmos_fifo_usb/smartgen\usb_fifo32x16"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS2X2M1
SMARTGEN_PACKAGE:vq100
WWIDTH:16
WDEPTH:16
RWIDTH:8
RDEPTH:32
CLKS:2
RESET_PN:RESET
RESET_POLARITY:0
INIT_RAM:F
DEFAULT_WORD:0x00
WCLK_EDGE:RISE
RCLK_EDGE:RISE
WCLOCK_PN:WCLK
RCLOCK_PN:RCLK
PMODE2:1
DATA_IN_PN:WD
WADDRESS_PN:WADDR
WE_PN:WEN
DATA_OUT_PN:RD
RADDRESS_PN:RADDR
RE_PN:REN
WE_POLARITY:0
RE_POLARITY:0
PTYPE:1