usb_fifo32x16.v

cmos数据到fifo再到usb的fifo部分程序(68013a)

`timescale 1 ns/100 ps
// Version: 8.0 8.0.0.40


module usb_fifo32x16(WD,RD,WEN,REN,WADDR,RADDR,WCLK,RCLK,RESET);
input [15:0] WD;
output [7:0] RD;
input  WEN, REN;
input [3:0] WADDR;
input [4:0] RADDR;
input WCLK, RCLK, RESET;

    wire VCC, GND;
    
    VCC VCC_1_net(.Y(VCC));
    GND GND_1_net(.Y(GND));
    RAM512X18 usb_fifo32x16_R0C0(.RADDR8(GND), .RADDR7(GND), 
        .RADDR6(GND), .RADDR5(GND), .RADDR4(RADDR[4]), .RADDR3(
        RADDR[3]), .RADDR2(RADDR[2]), .RADDR1(RADDR[1]), .RADDR0(
        RADDR[0]), .WADDR8(GND), .WADDR7(GND), .WADDR6(GND), 
        .WADDR5(GND), .WADDR4(GND), .WADDR3(WADDR[3]), .WADDR2(
        WADDR[2]), .WADDR1(WADDR[1]), .WADDR0(WADDR[0]), .WD17(
        GND), .WD16(WD[15]), .WD15(WD[14]), .WD14(WD[13]), .WD13(
        WD[12]), .WD12(WD[11]), .WD11(WD[10]), .WD10(WD[9]), .WD9(
        WD[8]), .WD8(GND), .WD7(WD[7]), .WD6(WD[6]), .WD5(WD[5]), 
        .WD4(WD[4]), .WD3(WD[3]), .WD2(WD[2]), .WD1(WD[1]), .WD0(
        WD[0]), .RW0(VCC), .RW1(GND), .WW0(GND), .WW1(VCC), .PIPE(
        VCC), .REN(REN), .WEN(WEN), .RCLK(RCLK), .WCLK(WCLK), 
        .RESET(RESET), .RD17(), .RD16(), .RD15(), .RD14(), .RD13()
        , .RD12(), .RD11(), .RD10(), .RD9(), .RD8(), .RD7(RD[7]), 
        .RD6(RD[6]), .RD5(RD[5]), .RD4(RD[4]), .RD3(RD[3]), .RD2(
        RD[2]), .RD1(RD[1]), .RD0(RD[0]));
    
endmodule

// _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._


// _GEN_File_Contents_

// Version:8.0.0.40
// ACTGENU_CALL:1
// BATCH:T
// FAM:ProASIC3
// OUTFORMAT:Verilog
// LPMTYPE:LPM_RAM
// LPM_HINT:TWO
// INSERT_PAD:NO
// INSERT_IOREG:NO
// GEN_BHV_VHDL_VAL:F
// GEN_BHV_VERILOG_VAL:F
// MGNTIMER:F
// MGNCMPL:T
// "DESDIR:H:/fpga_test/cmos_fifo_usb/smartgen\usb_fifo32x16"
// GEN_BEHV_MODULE:T
// SMARTGEN_DIE:IS2X2M1
// SMARTGEN_PACKAGE:vq100
// WWIDTH:16
// WDEPTH:16
// RWIDTH:8
// RDEPTH:32
// CLKS:2
// RESET_PN:RESET
// RESET_POLARITY:0
// INIT_RAM:F
// DEFAULT_WORD:0x00
// WCLK_EDGE:RISE
// RCLK_EDGE:RISE
// WCLOCK_PN:WCLK
// RCLOCK_PN:RCLK
// PMODE2:1
// DATA_IN_PN:WD
// WADDRESS_PN:WADDR
// WE_PN:WEN
// DATA_OUT_PN:RD
// RADDRESS_PN:RADDR
// RE_PN:REN
// WE_POLARITY:0
// RE_POLARITY:0
// PTYPE:1

// _End_Comments_