📄 two_port1280x8.v
字号:
`timescale 1 ns/100 ps
// Version: 8.0 8.0.0.40
module two_port1280x8(WD,RD,WEN,REN,WADDR,RADDR,WCLK,RCLK,RESET);
input [7:0] WD;
output [15:0] RD;
input WEN, REN;
input [10:0] WADDR;
input [9:0] RADDR;
input WCLK, RCLK, RESET;
wire ADDRA_FF2_0_net, ADDRA_FF2_1_net, ADDRB_FF1_0_net,
ADDRB_FF2_0_net, ADDRB_FF1_1_net, ADDRB_FF2_1_net,
ENABLE_ADDRA_0_net, ENABLE_ADDRA_1_net,
ENABLE_ADDRA_2_net, ENABLE_ADDRB_0_net,
ENABLE_ADDRB_1_net, ENABLE_ADDRB_2_net, BLKA_EN_0_net,
BLKB_EN_0_net, BLKA_EN_1_net, BLKB_EN_1_net,
BLKA_EN_2_net, BLKB_EN_2_net, QX_TEMPR0_0_net,
QX_TEMPR0_1_net, QX_TEMPR0_2_net, QX_TEMPR0_3_net,
QX_TEMPR0_4_net, QX_TEMPR0_5_net, QX_TEMPR0_6_net,
QX_TEMPR0_7_net, QX_TEMPR1_0_net, QX_TEMPR1_1_net,
QX_TEMPR1_2_net, QX_TEMPR1_3_net, QX_TEMPR1_4_net,
QX_TEMPR1_5_net, QX_TEMPR1_6_net, QX_TEMPR1_7_net,
QX_TEMPR2_0_net, QX_TEMPR2_1_net, QX_TEMPR2_2_net,
QX_TEMPR2_3_net, QX_TEMPR2_4_net, QX_TEMPR2_5_net,
QX_TEMPR2_6_net, QX_TEMPR2_7_net, QX_TEMPR0_8_net,
QX_TEMPR0_9_net, QX_TEMPR0_10_net, QX_TEMPR0_11_net,
QX_TEMPR0_12_net, QX_TEMPR0_13_net, QX_TEMPR0_14_net,
QX_TEMPR0_15_net, QX_TEMPR1_8_net, QX_TEMPR1_9_net,
QX_TEMPR1_10_net, QX_TEMPR1_11_net, QX_TEMPR1_12_net,
QX_TEMPR1_13_net, QX_TEMPR1_14_net, QX_TEMPR1_15_net,
QX_TEMPR2_8_net, QX_TEMPR2_9_net, QX_TEMPR2_10_net,
QX_TEMPR2_11_net, QX_TEMPR2_12_net, QX_TEMPR2_13_net,
QX_TEMPR2_14_net, QX_TEMPR2_15_net, MX2_4_Y, MX2_0_Y,
MX2_5_Y, MX2_6_Y, MX2_7_Y, MX2_2_Y, MX2_9_Y, MX2_14_Y,
MX2_13_Y, MX2_11_Y, MX2_15_Y, MX2_1_Y, MX2_3_Y, MX2_12_Y,
MX2_8_Y, MX2_10_Y, VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
MX2 MX2_RD_11_inst(.A(MX2_15_Y), .B(QX_TEMPR2_11_net), .S(
ADDRB_FF2_1_net), .Y(RD[11]));
OR2A OR2A_ENABLE_ADDRA_1_inst(.A(WADDR[9]), .B(WADDR[10]), .Y(
ENABLE_ADDRA_1_net));
OR2 ORB_GATE_0_inst(.A(ENABLE_ADDRB_0_net), .B(REN), .Y(
BLKB_EN_0_net));
RAM512X18 two_port1280x8_R1C0(.RADDR8(GND), .RADDR7(RADDR[7]),
.RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4(RADDR[4]),
.RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1(RADDR[1]),
.RADDR0(RADDR[0]), .WADDR8(WADDR[8]), .WADDR7(WADDR[7]),
.WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4(WADDR[4]),
.WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1(WADDR[1]),
.WADDR0(WADDR[0]), .WD17(GND), .WD16(GND), .WD15(GND),
.WD14(GND), .WD13(GND), .WD12(GND), .WD11(GND), .WD10(GND)
, .WD9(GND), .WD8(GND), .WD7(WD[7]), .WD6(WD[6]), .WD5(
WD[5]), .WD4(WD[4]), .WD3(WD[3]), .WD2(WD[2]), .WD1(WD[1])
, .WD0(WD[0]), .RW0(GND), .RW1(VCC), .WW0(VCC), .WW1(GND),
.PIPE(VCC), .REN(BLKB_EN_1_net), .WEN(BLKA_EN_1_net),
.RCLK(RCLK), .WCLK(WCLK), .RESET(RESET), .RD17(), .RD16(
QX_TEMPR1_15_net), .RD15(QX_TEMPR1_14_net), .RD14(
QX_TEMPR1_13_net), .RD13(QX_TEMPR1_12_net), .RD12(
QX_TEMPR1_11_net), .RD11(QX_TEMPR1_10_net), .RD10(
QX_TEMPR1_9_net), .RD9(QX_TEMPR1_8_net), .RD8(), .RD7(
QX_TEMPR1_7_net), .RD6(QX_TEMPR1_6_net), .RD5(
QX_TEMPR1_5_net), .RD4(QX_TEMPR1_4_net), .RD3(
QX_TEMPR1_3_net), .RD2(QX_TEMPR1_2_net), .RD1(
QX_TEMPR1_1_net), .RD0(QX_TEMPR1_0_net));
OR2 ORA_GATE_0_inst(.A(ENABLE_ADDRA_0_net), .B(WEN), .Y(
BLKA_EN_0_net));
MX2 MX2_RD_4_inst(.A(MX2_4_Y), .B(QX_TEMPR2_4_net), .S(
ADDRB_FF2_1_net), .Y(RD[4]));
MX2 MX2_RD_3_inst(.A(MX2_5_Y), .B(QX_TEMPR2_3_net), .S(
ADDRB_FF2_1_net), .Y(RD[3]));
MX2 MX2_RD_6_inst(.A(MX2_0_Y), .B(QX_TEMPR2_6_net), .S(
ADDRB_FF2_1_net), .Y(RD[6]));
MX2 MX2_9(.A(QX_TEMPR0_0_net), .B(QX_TEMPR1_0_net), .S(
ADDRB_FF2_0_net), .Y(MX2_9_Y));
DFN1 BFF2_0_inst(.D(ADDRB_FF1_0_net), .CLK(RCLK), .Q(
ADDRB_FF2_0_net));
MX2 MX2_0(.A(QX_TEMPR0_6_net), .B(QX_TEMPR1_6_net), .S(
ADDRB_FF2_0_net), .Y(MX2_0_Y));
OR2 OR2_ENABLE_ADDRA_0_inst(.A(WADDR[10]), .B(WADDR[9]), .Y(
ENABLE_ADDRA_0_net));
MX2 MX2_RD_15_inst(.A(MX2_1_Y), .B(QX_TEMPR2_15_net), .S(
ADDRB_FF2_1_net), .Y(RD[15]));
DFN1 BFF1_0_inst(.D(RADDR[8]), .CLK(RCLK), .Q(ADDRB_FF1_0_net)
);
MX2 MX2_11(.A(QX_TEMPR0_14_net), .B(QX_TEMPR1_14_net), .S(
ADDRB_FF2_0_net), .Y(MX2_11_Y));
MX2 MX2_6(.A(QX_TEMPR0_7_net), .B(QX_TEMPR1_7_net), .S(
ADDRB_FF2_0_net), .Y(MX2_6_Y));
OR2A OR2A_ENABLE_ADDRB_2_inst(.A(RADDR[9]), .B(RADDR[8]), .Y(
ENABLE_ADDRB_2_net));
MX2 MX2_RD_13_inst(.A(MX2_3_Y), .B(QX_TEMPR2_13_net), .S(
ADDRB_FF2_1_net), .Y(RD[13]));
DFN1 BFF1_1_inst(.D(RADDR[9]), .CLK(RCLK), .Q(ADDRB_FF1_1_net)
);
MX2 MX2_RD_5_inst(.A(MX2_7_Y), .B(QX_TEMPR2_5_net), .S(
ADDRB_FF2_1_net), .Y(RD[5]));
MX2 MX2_RD_2_inst(.A(MX2_2_Y), .B(QX_TEMPR2_2_net), .S(
ADDRB_FF2_1_net), .Y(RD[2]));
OR2A OR2A_ENABLE_ADDRB_1_inst(.A(RADDR[8]), .B(RADDR[9]), .Y(
ENABLE_ADDRB_1_net));
MX2 MX2_RD_10_inst(.A(MX2_12_Y), .B(QX_TEMPR2_10_net), .S(
ADDRB_FF2_1_net), .Y(RD[10]));
MX2 MX2_3(.A(QX_TEMPR0_13_net), .B(QX_TEMPR1_13_net), .S(
ADDRB_FF2_0_net), .Y(MX2_3_Y));
MX2 MX2_10(.A(QX_TEMPR0_9_net), .B(QX_TEMPR1_9_net), .S(
ADDRB_FF2_0_net), .Y(MX2_10_Y));
OR2 ORB_GATE_2_inst(.A(ENABLE_ADDRB_2_net), .B(REN), .Y(
BLKB_EN_2_net));
MX2 MX2_RD_1_inst(.A(MX2_14_Y), .B(QX_TEMPR2_1_net), .S(
ADDRB_FF2_1_net), .Y(RD[1]));
OR2 ORA_GATE_2_inst(.A(ENABLE_ADDRA_2_net), .B(WEN), .Y(
BLKA_EN_2_net));
MX2 MX2_RD_7_inst(.A(MX2_6_Y), .B(QX_TEMPR2_7_net), .S(
ADDRB_FF2_1_net), .Y(RD[7]));
MX2 MX2_RD_12_inst(.A(MX2_13_Y), .B(QX_TEMPR2_12_net), .S(
ADDRB_FF2_1_net), .Y(RD[12]));
MX2 MX2_4(.A(QX_TEMPR0_4_net), .B(QX_TEMPR1_4_net), .S(
ADDRB_FF2_0_net), .Y(MX2_4_Y));
OR2 OR2_ENABLE_ADDRB_0_inst(.A(RADDR[9]), .B(RADDR[8]), .Y(
ENABLE_ADDRB_0_net));
OR2A OR2A_ENABLE_ADDRA_2_inst(.A(WADDR[10]), .B(WADDR[9]), .Y(
ENABLE_ADDRA_2_net));
MX2 MX2_RD_9_inst(.A(MX2_10_Y), .B(QX_TEMPR2_9_net), .S(
ADDRB_FF2_1_net), .Y(RD[9]));
OR2 ORB_GATE_1_inst(.A(ENABLE_ADDRB_1_net), .B(REN), .Y(
BLKB_EN_1_net));
MX2 MX2_5(.A(QX_TEMPR0_3_net), .B(QX_TEMPR1_3_net), .S(
ADDRB_FF2_0_net), .Y(MX2_5_Y));
OR2 ORA_GATE_1_inst(.A(ENABLE_ADDRA_1_net), .B(WEN), .Y(
BLKA_EN_1_net));
RAM512X18 two_port1280x8_R2C0(.RADDR8(GND), .RADDR7(RADDR[7]),
.RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4(RADDR[4]),
.RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1(RADDR[1]),
.RADDR0(RADDR[0]), .WADDR8(WADDR[8]), .WADDR7(WADDR[7]),
.WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4(WADDR[4]),
.WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1(WADDR[1]),
.WADDR0(WADDR[0]), .WD17(GND), .WD16(GND), .WD15(GND),
.WD14(GND), .WD13(GND), .WD12(GND), .WD11(GND), .WD10(GND)
, .WD9(GND), .WD8(GND), .WD7(WD[7]), .WD6(WD[6]), .WD5(
WD[5]), .WD4(WD[4]), .WD3(WD[3]), .WD2(WD[2]), .WD1(WD[1])
, .WD0(WD[0]), .RW0(GND), .RW1(VCC), .WW0(VCC), .WW1(GND),
.PIPE(VCC), .REN(BLKB_EN_2_net), .WEN(BLKA_EN_2_net),
.RCLK(RCLK), .WCLK(WCLK), .RESET(RESET), .RD17(), .RD16(
QX_TEMPR2_15_net), .RD15(QX_TEMPR2_14_net), .RD14(
QX_TEMPR2_13_net), .RD13(QX_TEMPR2_12_net), .RD12(
QX_TEMPR2_11_net), .RD11(QX_TEMPR2_10_net), .RD10(
QX_TEMPR2_9_net), .RD9(QX_TEMPR2_8_net), .RD8(), .RD7(
QX_TEMPR2_7_net), .RD6(QX_TEMPR2_6_net), .RD5(
QX_TEMPR2_5_net), .RD4(QX_TEMPR2_4_net), .RD3(
QX_TEMPR2_3_net), .RD2(QX_TEMPR2_2_net), .RD1(
QX_TEMPR2_1_net), .RD0(QX_TEMPR2_0_net));
MX2 MX2_15(.A(QX_TEMPR0_11_net), .B(QX_TEMPR1_11_net), .S(
ADDRB_FF2_0_net), .Y(MX2_15_Y));
MX2 MX2_8(.A(QX_TEMPR0_8_net), .B(QX_TEMPR1_8_net), .S(
ADDRB_FF2_0_net), .Y(MX2_8_Y));
MX2 MX2_RD_0_inst(.A(MX2_9_Y), .B(QX_TEMPR2_0_net), .S(
ADDRB_FF2_1_net), .Y(RD[0]));
DFN1 AFF1_0_inst(.D(WADDR[9]), .CLK(WCLK), .Q(ADDRA_FF2_0_net)
);
MX2 MX2_RD_8_inst(.A(MX2_8_Y), .B(QX_TEMPR2_8_net), .S(
ADDRB_FF2_1_net), .Y(RD[8]));
MX2 MX2_2(.A(QX_TEMPR0_2_net), .B(QX_TEMPR1_2_net), .S(
ADDRB_FF2_0_net), .Y(MX2_2_Y));
RAM512X18 two_port1280x8_R0C0(.RADDR8(GND), .RADDR7(RADDR[7]),
.RADDR6(RADDR[6]), .RADDR5(RADDR[5]), .RADDR4(RADDR[4]),
.RADDR3(RADDR[3]), .RADDR2(RADDR[2]), .RADDR1(RADDR[1]),
.RADDR0(RADDR[0]), .WADDR8(WADDR[8]), .WADDR7(WADDR[7]),
.WADDR6(WADDR[6]), .WADDR5(WADDR[5]), .WADDR4(WADDR[4]),
.WADDR3(WADDR[3]), .WADDR2(WADDR[2]), .WADDR1(WADDR[1]),
.WADDR0(WADDR[0]), .WD17(GND), .WD16(GND), .WD15(GND),
.WD14(GND), .WD13(GND), .WD12(GND), .WD11(GND), .WD10(GND)
, .WD9(GND), .WD8(GND), .WD7(WD[7]), .WD6(WD[6]), .WD5(
WD[5]), .WD4(WD[4]), .WD3(WD[3]), .WD2(WD[2]), .WD1(WD[1])
, .WD0(WD[0]), .RW0(GND), .RW1(VCC), .WW0(VCC), .WW1(GND),
.PIPE(VCC), .REN(BLKB_EN_0_net), .WEN(BLKA_EN_0_net),
.RCLK(RCLK), .WCLK(WCLK), .RESET(RESET), .RD17(), .RD16(
QX_TEMPR0_15_net), .RD15(QX_TEMPR0_14_net), .RD14(
QX_TEMPR0_13_net), .RD13(QX_TEMPR0_12_net), .RD12(
QX_TEMPR0_11_net), .RD11(QX_TEMPR0_10_net), .RD10(
QX_TEMPR0_9_net), .RD9(QX_TEMPR0_8_net), .RD8(), .RD7(
QX_TEMPR0_7_net), .RD6(QX_TEMPR0_6_net), .RD5(
QX_TEMPR0_5_net), .RD4(QX_TEMPR0_4_net), .RD3(
QX_TEMPR0_3_net), .RD2(QX_TEMPR0_2_net), .RD1(
QX_TEMPR0_1_net), .RD0(QX_TEMPR0_0_net));
MX2 MX2_7(.A(QX_TEMPR0_5_net), .B(QX_TEMPR1_5_net), .S(
ADDRB_FF2_0_net), .Y(MX2_7_Y));
MX2 MX2_13(.A(QX_TEMPR0_12_net), .B(QX_TEMPR1_12_net), .S(
ADDRB_FF2_0_net), .Y(MX2_13_Y));
MX2 MX2_1(.A(QX_TEMPR0_15_net), .B(QX_TEMPR1_15_net), .S(
ADDRB_FF2_0_net), .Y(MX2_1_Y));
MX2 MX2_14(.A(QX_TEMPR0_1_net), .B(QX_TEMPR1_1_net), .S(
ADDRB_FF2_0_net), .Y(MX2_14_Y));
DFN1 AFF1_1_inst(.D(WADDR[10]), .CLK(WCLK), .Q(
ADDRA_FF2_1_net));
DFN1 BFF2_1_inst(.D(ADDRB_FF1_1_net), .CLK(RCLK), .Q(
ADDRB_FF2_1_net));
MX2 MX2_RD_14_inst(.A(MX2_11_Y), .B(QX_TEMPR2_14_net), .S(
ADDRB_FF2_1_net), .Y(RD[14]));
MX2 MX2_12(.A(QX_TEMPR0_10_net), .B(QX_TEMPR1_10_net), .S(
ADDRB_FF2_0_net), .Y(MX2_12_Y));
endmodule
// _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._
// _GEN_File_Contents_
// Version:8.0.0.40
// ACTGENU_CALL:1
// BATCH:T
// FAM:ProASIC3
// OUTFORMAT:Verilog
// LPMTYPE:LPM_RAM
// LPM_HINT:TWO
// INSERT_PAD:NO
// INSERT_IOREG:NO
// GEN_BHV_VHDL_VAL:F
// GEN_BHV_VERILOG_VAL:F
// MGNTIMER:F
// MGNCMPL:T
// "DESDIR:E:/fpga_test/cmos_fifo_usb/smartgen\two_port1280x8"
// GEN_BEHV_MODULE:T
// SMARTGEN_DIE:IS2X2M1
// SMARTGEN_PACKAGE:vq100
// WWIDTH:8
// WDEPTH:1280
// RWIDTH:16
// RDEPTH:640
// CLKS:2
// RESET_PN:RESET
// RESET_POLARITY:0
// INIT_RAM:F
// DEFAULT_WORD:0x0000
// WCLK_EDGE:RISE
// RCLK_EDGE:RISE
// WCLOCK_PN:WCLK
// RCLOCK_PN:RCLK
// PMODE2:1
// DATA_IN_PN:WD
// WADDRESS_PN:WADDR
// WE_PN:WEN
// DATA_OUT_PN:RD
// RADDRESS_PN:RADDR
// RE_PN:REN
// WE_POLARITY:0
// RE_POLARITY:0
// PTYPE:1
// _End_Comments_
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