two_port1280x8.log

cmos数据到fifo再到usb的fifo部分程序(68013a)

 ** Message System Log
 ** Database: 
 ** Date:   Tue May 20 23:08:50 2008


****************
Macro Parameters
****************

Name                            : two_port1280x8
Family                          : ProASIC3
Output Format                   : VERILOG
Type                            : RAM
Write Enable                    : Active Low
Read Enable                     : Active Low
Reset                           : Active Low
Read Clock                      : Rising
Write Clock                     : Rising
Write Depth                     : 1280
Write Width                     : 8
Read Depth                      : 640
Read Width                      : 16
RAM Type                        : Two Port
Clocks                          : Independent Read and Write Clocks
Write Mode A                    : Hold Data
Write Mode B                    : Hold Data
Read Pipeline A                 : No
Read Pipeline B                 : Yes
Portname DataIn                 : WD
Portname DataOut                : RD
Portname Write En               : WEN
Portname Read En                : REN
Portname WClock                 : WCLK
Portname RClock                 : RCLK
Portname WAddress               : WADDR
Portname RAddress               : RADDR
Portname Reset                  : RESET
Portname Clock                  :
Portname DataAIn                :
Portname DataBIn                :
Portname DataAOut               :
Portname DataBOut               :
Portname AddressA               :
Portname AddressB               :
Portname CLKA                   :
Portname CLKB                   :
Portname RWA                    :
Portname RWB                    :
Portname BLKA                   :
Portname BLKB                   :
Initialize RAM                  : False

Cascade Configuration:
     Write Port configuration   : 512x9
     Read Port configuration    : 256x18
     Number of blocks depth wise: 3
     Number of blocks width wise: 1

**************
Compile Report
**************


Netlist Resource Report
=======================

    CORE                     Used:     44
    IO (W/ clocks)           Used:      0
    Low Static ICC           Used:      0
    FlashROM                 Used:      0
    User JTAG                Used:      0

Written Verilog netlist to
E:/fpga_test/cmos_fifo_usb/smartgen\two_port1280x8\two_port1280x8.v.

 ** Log Ended:   Tue May 20 23:08:51 2008