two_port1280x8.cxf

cmos数据到fifo再到usb的fifo部分程序(68013a)

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>two_port1280x8</name><fileSets><fileSet fileSetId="HDL_FILESET"><file fileId="1"><name>two_port1280x8.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileId="2"><name>two_port1280x8.gen</name><fileType><userFileType type="GEN"/></fileType></file><file fileId="3"><name>two_port1280x8.log</name><fileType><userFileType type="LOG"/></fileType></file><file fileId="4"><name>two_port1280x8.shx</name><fileType><userFileType type="Other"/></fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileId="5"><name>two_port1280x8_R0C0.mem</name><fileType><userFileType type="MEM"/></fileType></file><file fileId="6"><name>two_port1280x8_R1C0.mem</name><fileType><userFileType type="MEM"/></fileType></file><file fileId="7"><name>two_port1280x8_R2C0.mem</name><fileType><userFileType type="MEM"/></fileType></file></fileSet></fileSets><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>Other</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>Simulation</name></view></views><category>RAM</category><function>RAM</function><variation>Two Port RAM</variation><vendor>Actel</vendor><version>2.1</version><model><signals><signal><name>WD</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>RD</name><direction>out</direction><left>15</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>WEN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>REN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>WADDR</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>RADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>WCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>RCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>RESET</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal></signals></model></Component>