soft_fifo1280x8.log

cmos数据到fifo再到usb的fifo部分程序(68013a)

 ** Message System Log
 ** Database: 
 ** Date:   Tue May 20 17:20:38 2008


****************
Macro Parameters
****************

Name                            : soft_fifo1280x8
Family                          : ProASIC3
Output Format                   : VERILOG
Type                            : SOFTFIFO
Write Enable                    : Active Low
Read Clock                      : Rising
Write Clock                     : Rising
Reset                           : Active Low
Read Enable                     : Active Low
Write Depth                     : 1280
Write Width                     : 8
Read Depth                      : 640
Read Width                      : 16
Almost Full                     : 65536
Almost Empty                    : 65536
Clocks                          : Independent Read and Write Clocks
AEFlag                          : None
AFFlag                          : None
Read Pipe Mode1                 : No Pipe
Prevent Read When Empty         : Yes
Prevent Write When Full         : Yes
Write Acknowledge               : No
Data Valid                      : No
Overflow                        : No
Underflow                       : No
Read Data Count                 : No
Write Data Count                : No
Standalone Controller           : False
Initialize RAM                  : False
Portname DataIn                 : DATA
Portname DataOut                : Q
Portname AE Port                : AEVAL
Portname AF Port                : AFVAL
Portname Write En               : WE
Portname Read En                : RE
Portname WClock                 : WCLOCK
Portname RClock                 : RCLOCK
Portname AE Flag                : AEMPTY
Portname AF Flag                : AFULL
Portname Full Flag              : FULL
Portname Empty Flag             : EMPTY
Portname Reset                  : RESET
Portname Write Acknowledge      : WACK
Portname Data Valid             : DVLD
Portname Overflow               : OVERFLOW
Portname Underflow              : UNDERFLOW
Portname Read Count             : RDCNT
Portname Write Count            : WRCNT
Portname Memory Write Address   :
Portname Memory Read Address    :
Portname Memory Write Enable    :
Portname Memory Read Enable     :
Portname Clock                  :

Cascade Configuration:
     Write Port configuration   : 512x9
     Read Port configuration    : 256x18
     Number of blocks depth wise: 3
     Number of blocks width wise: 1

**************
Compile Report
**************

Warning:  CMP503: Remapped 39 enable flip-flop(s) to a 2-tile implementation
          because the CLR/PRE pin on the enable flip-flop is not being driven
          by a global net.

Netlist Resource Report
=======================

    CORE                     Used:    598
    IO (W/ clocks)           Used:      0
    Low Static ICC           Used:      0
    FlashROM                 Used:      0
    User JTAG                Used:      0

Written Verilog netlist to
H:/fpga_test/cmos_fifo_usb/smartgen\soft_fifo1280x8\soft_fifo1280x8.v.

 ** Log Ended:   Tue May 20 17:20:40 2008