soft_fifo1280x8.v

cmos数据到fifo再到usb的fifo部分程序(68013a)

    XNOR2 XNOR2_0(.A(FULLCONSTVALUE_0_net), .B(WDIFF_7_net), .Y(
        XNOR2_0_Y));
    RAM512X18 RAM512X18_2(.RADDR8(GND), .RADDR7(MEM_RADDR_7_net), 
        .RADDR6(MEM_RADDR_6_net), .RADDR5(MEM_RADDR_5_net), 
        .RADDR4(MEM_RADDR_4_net), .RADDR3(MEM_RADDR_3_net), 
        .RADDR2(MEM_RADDR_2_net), .RADDR1(MEM_RADDR_1_net), 
        .RADDR0(MEM_RADDR_0_net), .WADDR8(MEM_WADDR_8_net), 
        .WADDR7(MEM_WADDR_7_net), .WADDR6(MEM_WADDR_6_net), 
        .WADDR5(MEM_WADDR_5_net), .WADDR4(MEM_WADDR_4_net), 
        .WADDR3(MEM_WADDR_3_net), .WADDR2(MEM_WADDR_2_net), 
        .WADDR1(MEM_WADDR_1_net), .WADDR0(MEM_WADDR_0_net), .WD17(
        GND), .WD16(GND), .WD15(GND), .WD14(GND), .WD13(GND), 
        .WD12(GND), .WD11(GND), .WD10(GND), .WD9(GND), .WD8(GND), 
        .WD7(DATA[7]), .WD6(DATA[6]), .WD5(DATA[5]), .WD4(DATA[4])
        , .WD3(DATA[3]), .WD2(DATA[2]), .WD1(DATA[1]), .WD0(
        DATA[0]), .RW0(GND), .RW1(VCC), .WW0(VCC), .WW1(GND), 
        .PIPE(GND), .REN(OR2_4_Y), .WEN(OR2_3_Y), .RCLK(RCLOCK), 
        .WCLK(WCLOCK), .RESET(RESET), .RD17(), .RD16(
        RAM512X18_2_RD16), .RD15(RAM512X18_2_RD15), .RD14(
        RAM512X18_2_RD14), .RD13(RAM512X18_2_RD13), .RD12(
        RAM512X18_2_RD12), .RD11(RAM512X18_2_RD11), .RD10(
        RAM512X18_2_RD10), .RD9(RAM512X18_2_RD9), .RD8(), .RD7(
        RAM512X18_2_RD7), .RD6(RAM512X18_2_RD6), .RD5(
        RAM512X18_2_RD5), .RD4(RAM512X18_2_RD4), .RD3(
        RAM512X18_2_RD3), .RD2(RAM512X18_2_RD2), .RD1(
        RAM512X18_2_RD1), .RD0(RAM512X18_2_RD0));
    XNOR2 XNOR2_41(.A(RDADDRGEN_CONST_0_net), .B(MEM_RADDR_1_net), 
        .Y(XNOR2_41_Y));
    XOR2 XOR2_RBINNXT_8_inst(.A(XOR2_61_Y), .B(AO1_8_Y), .Y(
        RBINNXT_8_net));
    AND3 AND3_11(.A(XNOR2_32_Y), .B(XNOR2_10_Y), .C(XNOR2_43_Y), 
        .Y(AND3_11_Y));
    XNOR2 XNOR2_15(.A(FULLCONSTVALUE_0_net), .B(WDIFF_6_net), .Y(
        XNOR2_15_Y));
    XOR2 XOR2_66(.A(WBINNXT_9_net), .B(INV_19_Y), .Y(XOR2_66_Y));
    XNOR3 XNOR3_20(.A(XNOR3_10_Y), .B(XNOR3_13_Y), .C(XNOR3_15_Y), 
        .Y(XNOR3_20_Y));
    XNOR2 XNOR2_WBINSYNC_4_inst(.A(XNOR3_21_Y), .B(XNOR3_34_Y), 
        .Y(WBINSYNC_4_net));
    AO1 AO1_42(.A(XOR2_27_Y), .B(AO1_6_Y), .C(AND2_42_Y), .Y(
        AO1_42_Y));
    AND2 AND2_37(.A(RBIN_4_net), .B(GND), .Y(AND2_37_Y));
    AO1 AO1_18(.A(AND2_12_Y), .B(AO1_37_Y), .C(AO1_53_Y), .Y(
        AO1_18_Y));
    INV INV_10(.A(RBINSYNC_10_net), .Y(INV_10_Y));
    XNOR2 XNOR2_20(.A(RDADDRGEN_CONST_7_net), .B(MEM_RADDR_9_net), 
        .Y(XNOR2_20_Y));
    RAM512X18 RAM512X18_0(.RADDR8(GND), .RADDR7(MEM_RADDR_7_net), 
        .RADDR6(MEM_RADDR_6_net), .RADDR5(MEM_RADDR_5_net), 
        .RADDR4(MEM_RADDR_4_net), .RADDR3(MEM_RADDR_3_net), 
        .RADDR2(MEM_RADDR_2_net), .RADDR1(MEM_RADDR_1_net), 
        .RADDR0(MEM_RADDR_0_net), .WADDR8(MEM_WADDR_8_net), 
        .WADDR7(MEM_WADDR_7_net), .WADDR6(MEM_WADDR_6_net), 
        .WADDR5(MEM_WADDR_5_net), .WADDR4(MEM_WADDR_4_net), 
        .WADDR3(MEM_WADDR_3_net), .WADDR2(MEM_WADDR_2_net), 
        .WADDR1(MEM_WADDR_1_net), .WADDR0(MEM_WADDR_0_net), .WD17(
        GND), .WD16(GND), .WD15(GND), .WD14(GND), .WD13(GND), 
        .WD12(GND), .WD11(GND), .WD10(GND), .WD9(GND), .WD8(GND), 
        .WD7(DATA[7]), .WD6(DATA[6]), .WD5(DATA[5]), .WD4(DATA[4])
        , .WD3(DATA[3]), .WD2(DATA[2]), .WD1(DATA[1]), .WD0(
        DATA[0]), .RW0(GND), .RW1(VCC), .WW0(VCC), .WW1(GND), 
        .PIPE(GND), .REN(OR2_1_Y), .WEN(OR2_7_Y), .RCLK(RCLOCK), 
        .WCLK(WCLOCK), .RESET(RESET), .RD17(), .RD16(
        RAM512X18_0_RD16), .RD15(RAM512X18_0_RD15), .RD14(
        RAM512X18_0_RD14), .RD13(RAM512X18_0_RD13), .RD12(
        RAM512X18_0_RD12), .RD11(RAM512X18_0_RD11), .RD10(
        RAM512X18_0_RD10), .RD9(RAM512X18_0_RD9), .RD8(), .RD7(
        RAM512X18_0_RD7), .RD6(RAM512X18_0_RD6), .RD5(
        RAM512X18_0_RD5), .RD4(RAM512X18_0_RD4), .RD3(
        RAM512X18_0_RD3), .RD2(RAM512X18_0_RD2), .RD1(
        RAM512X18_0_RD1), .RD0(RAM512X18_0_RD0));
    DFN1C0 DFN1C0_16(.D(RGRY_5_net), .CLK(WCLOCK), .CLR(RESET), 
        .Q(DFN1C0_16_Q));
    DFN1E1C0 DFN1E1C0_Q_5_inst(.D(QXI_5_net), .CLK(RCLOCK), .CLR(
        RESET), .E(DVLDI), .Q(Q[5]));
    AO1 AO1_39(.A(AND2_50_Y), .B(AO1_41_Y), .C(AO1_33_Y), .Y(
        AO1_39_Y));
    XNOR3 XNOR3_21(.A(WGRYSYNC_8_net), .B(WGRYSYNC_7_net), .C(
        WGRYSYNC_6_net), .Y(XNOR3_21_Y));
    DFN1C0 DFN1C0_12(.D(RGRY_2_net), .CLK(WCLOCK), .CLR(RESET), 
        .Q(DFN1C0_12_Q));
    XOR2 XOR2_41(.A(WBINNXT_5_net), .B(WBINNXT_6_net), .Y(
        XOR2_41_Y));
    AO1 AO1_21(.A(XOR2_75_Y), .B(AO1_13_Y), .C(AND2_22_Y), .Y(
        AO1_21_Y));
    XOR2 XOR2_7(.A(WBINSYNC_10_net), .B(INV_21_Y), .Y(XOR2_7_Y));
    DFN1E1C0 DFN1E1C0_Q_8_inst(.D(QXI_8_net), .CLK(RCLOCK), .CLR(
        RESET), .E(DVLDI), .Q(Q[8]));
    INV REBUBBLE(.A(RE), .Y(REP));
    INV INV_15(.A(RBINNXT_10_net), .Y(INV_15_Y));
    XOR2 XOR2_54(.A(WBINNXT_10_net), .B(INV_18_Y), .Y(XOR2_54_Y));
    MAJ3 MAJ3_1(.A(MAJ3_18_Y), .B(MEM_WADDR_2_net), .C(GND), .Y(
        MAJ3_1_Y));
    AND3 AND3_9(.A(XNOR2_8_Y), .B(XNOR2_42_Y), .C(XNOR2_28_Y), .Y(
        AND3_9_Y));
    XNOR2 XNOR2_RBINSYNC_7_inst(.A(RGRYSYNC_7_net), .B(XNOR3_0_Y), 
        .Y(RBINSYNC_7_net));
    XNOR2 XNOR2_21(.A(RDADDRGEN_CONST_0_net), .B(MEM_RADDR_5_net), 
        .Y(XNOR2_21_Y));
    AND2 AND2_44(.A(AND2_16_Y), .B(XOR2_50_Y), .Y(AND2_44_Y));
    XNOR3 XNOR3_13(.A(WGRYSYNC_8_net), .B(WGRYSYNC_7_net), .C(
        WGRYSYNC_6_net), .Y(XNOR3_13_Y));
    XOR3 XOR3_14(.A(MEM_RADDR_5_net), .B(GND), .C(MAJ3_4_Y), .Y(
        XOR3_14_Y));
    AND3 AND3_16(.A(XNOR2_3_Y), .B(XNOR2_41_Y), .C(XNOR2_24_Y), 
        .Y(AND3_16_Y));
    DFN1C0 DFN1C0_WGRY_8_inst(.D(XOR2_0_Y), .CLK(WCLOCK), .CLR(
        RESET), .Q(WGRY_8_net));
    XOR2 XOR2_RBINNXT_0_inst(.A(RBIN_0_net), .B(MEMORYRE), .Y(
        RBINNXT_0_net));
    XOR2 XOR2_WBINSYNC_10_inst(.A(WGRYSYNC_11_net), .B(
        WGRYSYNC_10_net), .Y(WBINSYNC_10_net));
    DFN1C0 DFN1C0_18(.D(RGRY_8_net), .CLK(WCLOCK), .CLR(RESET), 
        .Q(DFN1C0_18_Q));
    XOR2 XOR2_23(.A(WBINNXT_3_net), .B(INV_23_Y), .Y(XOR2_23_Y));
    DFN1C0 DFN1C0_WBIN_3_inst(.D(WBINNXT_3_net), .CLK(WCLOCK), 
        .CLR(RESET), .Q(WBIN_3_net));
    XOR2 XOR2_33(.A(WBINNXT_2_net), .B(WBINNXT_3_net), .Y(
        XOR2_33_Y));
    AND2 AND2_31(.A(WBIN_2_net), .B(GND), .Y(AND2_31_Y));
    XNOR2 XNOR2_WDIFF_1_inst(.A(XOR2_53_Y), .B(NOR2A_1_Y), .Y(
        WDIFF_1_net));
    XOR2 XOR2_29(.A(WBINSYNC_9_net), .B(INV_22_Y), .Y(XOR2_29_Y));
    AND2 AND2_64(.A(AND2_84_Y), .B(XOR2_75_Y), .Y(AND2_64_Y));
    XOR2 XOR2_39(.A(WBINNXT_9_net), .B(WBINNXT_10_net), .Y(
        XOR2_39_Y));
    OR2A OR2A_12(.A(EMPTYVALUECONST_0_net), .B(RDIFF_5_net), .Y(
        OR2A_12_Y));
    OR2A OR2A_0(.A(RDIFF_5_net), .B(EMPTYVALUECONST_0_net), .Y(
        OR2A_0_Y));
    DFN1C0 DFN1C0_RGRY_9_inst(.D(XOR2_57_Y), .CLK(RCLOCK), .CLR(
        RESET), .Q(RGRY_9_net));
    AND2 AND2_19(.A(XOR2_4_Y), .B(XOR2_92_Y), .Y(AND2_19_Y));
    XNOR3 XNOR3_RBINSYNC_4_inst(.A(RGRYSYNC_4_net), .B(XOR3_23_Y), 
        .C(XNOR3_11_Y), .Y(RBINSYNC_4_net));
    AND2 AND2_79(.A(XOR2_79_Y), .B(XOR2_21_Y), .Y(AND2_79_Y));
    DFN1C0 DFN1C0_WGRY_1_inst(.D(XOR2_34_Y), .CLK(WCLOCK), .CLR(
        RESET), .Q(WGRY_1_net));
    XOR2 XOR2_27(.A(WBINNXT_11_net), .B(INV_10_Y), .Y(XOR2_27_Y));
    MX2 MX2_8(.A(RAM512X18_0_RD1), .B(RAM512X18_1_RD1), .S(
        DFN1_1_Q), .Y(MX2_8_Y));
    XOR2 XOR2_6(.A(WBIN_4_net), .B(GND), .Y(XOR2_6_Y));
    XOR2 XOR2_37(.A(WBIN_8_net), .B(GND), .Y(XOR2_37_Y));
    AND2 AND2_115(.A(XOR2_18_Y), .B(XOR2_48_Y), .Y(AND2_115_Y));
    DFN1C0 DFN1C0_WBIN_1_inst(.D(WBINNXT_1_net), .CLK(WCLOCK), 
        .CLR(RESET), .Q(WBIN_1_net));
    XOR2 XOR2_55(.A(WBIN_5_net), .B(GND), .Y(XOR2_55_Y));
    OR2A OR2A_16(.A(EMPTYVALUECONST_0_net), .B(RDIFF_2_net), .Y(
        OR2A_16_Y));
    INV INV_19(.A(RBINSYNC_8_net), .Y(INV_19_Y));
    AND2A AND2A_2(.A(EMPTY), .B(REP), .Y(AND2A_2_Y));
    XOR2 XOR2_109(.A(RBINNXT_0_net), .B(RBINNXT_1_net), .Y(
        XOR2_109_Y));
    AND2 AND2_104(.A(XOR2_9_Y), .B(XOR2_83_Y), .Y(AND2_104_Y));
    AND2 AND2_36(.A(XOR2_25_Y), .B(XOR2_68_Y), .Y(AND2_36_Y));
    AND2 AND2_9(.A(XOR2_67_Y), .B(XOR2_102_Y), .Y(AND2_9_Y));
    XNOR2 XNOR2_16(.A(RDADDRGEN_CONST_0_net), .B(MEM_RADDR_3_net), 
        .Y(XNOR2_16_Y));
    AND2A AND2A_1(.A(AND3_2_Y), .B(MEMORYRE), .Y(AND2A_1_Y));
    DFN1C0 DFN1C0_WGRY_5_inst(.D(XOR2_41_Y), .CLK(WCLOCK), .CLR(
        RESET), .Q(WGRY_5_net));
    DFN1C0 DFN1C0_WBIN_0_inst(.D(WBINNXT_0_net), .CLK(WCLOCK), 
        .CLR(RESET), .Q(WBIN_0_net));
    XOR3 XOR3_15(.A(MEM_RADDR_6_net), .B(GND), .C(MAJ3_13_Y), .Y(
        XOR3_15_Y));
    XNOR2 XNOR2_32(.A(RDIFF_6_net), .B(EMPTYVALUECONST_0_net), .Y(
        XNOR2_32_Y));
    AND2 AND2_110(.A(WBINNXT_5_net), .B(INV_11_Y), .Y(AND2_110_Y));
    RAM512X18 RAM512X18_1(.RADDR8(GND), .RADDR7(MEM_RADDR_7_net), 
        .RADDR6(MEM_RADDR_6_net), .RADDR5(MEM_RADDR_5_net), 
        .RADDR4(MEM_RADDR_4_net), .RADDR3(MEM_RADDR_3_net), 
        .RADDR2(MEM_RADDR_2_net), .RADDR1(MEM_RADDR_1_net), 
        .RADDR0(MEM_RADDR_0_net), .WADDR8(MEM_WADDR_8_net), 
        .WADDR7(MEM_WADDR_7_net), .WADDR6(MEM_WADDR_6_net), 
        .WADDR5(MEM_WADDR_5_net), .WADDR4(MEM_WADDR_4_net), 
        .WADDR3(MEM_WADDR_3_net), .WADDR2(MEM_WADDR_2_net), 
        .WADDR1(MEM_WADDR_1_net), .WADDR0(MEM_WADDR_0_net), .WD17(
        GND), .WD16(GND), .WD15(GND), .WD14(GND), .WD13(GND), 
        .WD12(GND), .WD11(GND), .WD10(GND), .WD9(GND), .WD8(GND), 
        .WD7(DATA[7]), .WD6(DATA[6]), .WD5(DATA[5]), .WD4(DATA[4])
        , .WD3(DATA[3]), .WD2(DATA[2]), .WD1(DATA[1]), .WD0(
        DATA[0]), .RW0(GND), .RW1(VCC), .WW0(VCC), .WW1(GND), 
        .PIPE(GND), .REN(OR2_2_Y), .WEN(OR2_0_Y), .RCLK(RCLOCK), 
        .WCLK(WCLOCK), .RESET(RESET), .RD17(), .RD16(
        RAM512X18_1_RD16), .RD15(RAM512X18_1_RD15), .RD14(
        RAM512X18_1_RD14), .RD13(RAM512X18_1_RD13), .RD12(
        RAM512X18_1_RD12), .RD11(RAM512X18_1_RD11), .RD10(
        RAM512X18_1_RD10), .RD9(RAM512X18_1_RD9), .RD8(), .RD7(
        RAM512X18_1_RD7), .RD6(RAM512X18_1_RD6), .RD5(
        RAM512X18_1_RD5), .RD4(RAM512X18_1_RD4), .RD3(
        RAM512X18_1_RD3), .RD2(RAM512X18_1_RD2), .RD1(
        RAM512X18_1_RD1), .RD0(RAM512X18_1_RD0));
    INV INV_24(.A(RBINNXT_3_net), .Y(INV_24_Y));
    AND2 AND2_101(.A(WBINSYNC_9_net), .B(INV_22_Y), .Y(AND2_101_Y)
        );
    DFN1C0 DFN1C0_RGRYSYNC_10_inst(.D(DFN1C0_5_Q), .CLK(WCLOCK), 
        .CLR(RESET), .Q(RGRYSYNC_10_net));
    AO1 AO1_47(.A(XOR2_16_Y), .B(AND2_110_Y), .C(AND2_28_Y), .Y(
        AO1_47_Y));
    XNOR2 XNOR2_RBINSYNC_5_inst(.A(XOR3_12_Y), .B(XNOR3_28_Y), .Y(
        RBINSYNC_5_net));
    XNOR3 XNOR3_30(.A(WGRYSYNC_2_net), .B(WGRYSYNC_1_net), .C(
        XOR3_25_Y), .Y(XNOR3_30_Y));
    XOR2 XOR2_RDIFF_4_inst(.A(XOR2_93_Y), .B(AO1_38_Y), .Y(
        RDIFF_4_net));
    DFN1E1C0 DFN1E1C0_Q_3_inst(.D(QXI_3_net), .CLK(RCLOCK), .CLR(
        RESET), .E(DVLDI), .Q(Q[3]));
    DFN1C0 DFN1C0_RBIN_10_inst(.D(RBINNXT_10_net), .CLK(RCLOCK), 
        .CLR(RESET), .Q(RBIN_10_net));
    AND2 AND2_10(.A(INV_5_Y), .B(INV_6_Y), .Y(AND2_10_Y));
    XOR2 XOR2_WBINNXT_7_inst(.A(XOR2_103_Y), .B(AO1_9_Y), .Y(
        WBINNXT_7_net));
    AND2 AND2_70(.A(WBINNXT_8_net), .B(INV_20_Y), .Y(AND2_70_Y));
    XOR3 XOR3_WBINSYNC_9_inst(.A(WGRYSYNC_11_net), .B(
        WGRYSYNC_10_net), .C(WGRYSYNC_9_net), .Y(WBINSYNC_9_net));
    MAJ3 MAJ3_16(.A(MAJ3_11_Y), .B(MEM_WADDR_4_net), .C(GND), .Y(
        MAJ3_16_Y));
    XOR2 XOR2_RBINNXT_1_inst(.A(XOR2_3_Y), .B(AND2_40_Y), .Y(
        RBINNXT_1_net));
    XNOR2 XNOR2_7(.A(WRADDRGEN_CONST_0_net), .B(MEM_WADDR_7_net), 
        .Y(XNOR2_7_Y));
    AO1 AO1_48(.A(AND2_104_Y), .B(AO1_8_Y), .C(AO1_20_Y), .Y(
        AO1_48_Y));
    XNOR3 XNOR3_31(.A(RGRYSYNC_7_net), .B(RGRYSYNC_6_net), .C(
        RGRYSYNC_5_net), .Y(XNOR3_31_Y));
    XNOR3 XNOR3_29(.A(WGRYSYNC_8_net), .B(WGRYSYNC_7_net), .C(
        WGRYSYNC_6_net), .Y(XNOR3_29_Y));
    INV INV_22(.A(RBINNXT_8_net), .Y(INV_22_Y));
    NOR3A NOR3A_5(.A(OR2A_17_Y), .B(AO1C_5_Y), .C(WDIFF_0_net), 
        .Y(NOR3A_5_Y));
    XOR2 XOR2_42(.A(RBIN_7_net), .B(GND), .Y(XOR2_42_Y));
    XNOR3 XNOR3_7(.A(WGRYSYNC_5_net), .B(WGRYSYNC_4_net), .C(
        WGRYSYNC_3_net), .Y(XNOR3_7_Y));
    DFN1C0 DFN1C0_FULL(.D(AOI1_1_Y), .CLK(WCLOCK), .CLR(RESET), 
        .Q(FULL));
    AO1 AO1_36(.A(XOR2_47_Y), .B(AND2_30_Y), .C(AND2_62_Y), .Y(
        AO1_36_Y));
    DFN1C0 DFN1C0_WBIN_11_inst(.D(WBINNXT_11_net), .CLK(WCLOCK), 
        .CLR(RESET), .Q(WBIN_11_net));
    DFN1C0 DFN1C0_RBIN_7_inst(.D(RBINNXT_7_net), .CLK(RCLOCK), 
        .CLR(RESET), .Q(RBIN_7_net));
    XOR2 XOR2_50(.A(WBINNXT_5_net), .B(INV_11_Y), .Y(XOR2_50_Y));
    XNOR2 XNOR2_29(.A(EMPTYVALUECONST_0_net), .B(RDIFF_3_net), .Y(
        XNOR2_29_Y));
    NOR3A NOR3A_1(.A(OR2A_6_Y), .B(AO1C_2_Y), .C(WDIFF_9_net), .Y(
        NOR3A_1_Y));
    DFN1E1C0 DFN1E1C0_MEM_RADDR_7_inst(.D(XOR3_27_Y), .CLK(RCLOCK)
        , .CLR(AND2_41_Y), .E(AND2A_1_Y), .Q(MEM_RADDR_7_net));
    XNOR3 XNOR3_12(.A(WGRYSYNC_2_net), .B(XOR3_11_Y), .C(
        XNOR3_2_Y), .Y(XNOR3_12_Y));
    XOR2 XOR2_0(.A(WBINNXT_8_net), .B(WBINNXT_9_net), .Y(XOR2_0_Y)