soft_fifo1280x8.v

cmos数据到fifo再到usb的fifo部分程序(68013a)

    XOR2 XOR2_40(.A(WBIN_10_net), .B(GND), .Y(XOR2_40_Y));
    AND2 AND2_91(.A(WBIN_7_net), .B(GND), .Y(AND2_91_Y));
    AO1 AO1_54(.A(AND2_94_Y), .B(AO1_57_Y), .C(AO1_34_Y), .Y(
        AO1_54_Y));
    BUFF BUFF_WBINSYNC_11_inst(.A(WGRYSYNC_11_net), .Y(
        WBINSYNC_11_net));
    OR2A OR2A_13(.A(RDIFF_8_net), .B(EMPTYVALUECONST_0_net), .Y(
        OR2A_13_Y));
    INV INV_9(.A(NOR2A_1_Y), .Y(INV_9_Y));
    XNOR3 XNOR3_27(.A(RGRYSYNC_7_net), .B(RGRYSYNC_6_net), .C(
        RGRYSYNC_5_net), .Y(XNOR3_27_Y));
    DFN1C0 DFN1C0_RGRY_4_inst(.D(XOR2_88_Y), .CLK(RCLOCK), .CLR(
        RESET), .Q(RGRY_4_net));
    AND2 AND2_69(.A(XOR2_100_Y), .B(XOR2_77_Y), .Y(AND2_69_Y));
    XOR2 XOR2_92(.A(WBINSYNC_3_net), .B(INV_3_Y), .Y(XOR2_92_Y));
    XNOR2 XNOR2_27(.A(WRADDRGEN_CONST_0_net), .B(MEM_WADDR_11_net)
        , .Y(XNOR2_27_Y));
    XOR2 XOR2_RBINNXT_9_inst(.A(XOR2_87_Y), .B(AO1_0_Y), .Y(
        RBINNXT_9_net));
    AND2 AND2_55(.A(RBIN_8_net), .B(GND), .Y(AND2_55_Y));
    AND3 AND3_12(.A(XNOR2_2_Y), .B(XNOR2_37_Y), .C(XNOR2_36_Y), 
        .Y(AND3_12_Y));
    XNOR3 XNOR3_15(.A(WGRYSYNC_5_net), .B(WGRYSYNC_4_net), .C(
        WGRYSYNC_3_net), .Y(XNOR3_15_Y));
    MAJ3 MAJ3_18(.A(AND2_25_Y), .B(MEM_WADDR_1_net), .C(GND), .Y(
        MAJ3_18_Y));
    DFN1C0 DFN1C0_WGRYSYNC_3_inst(.D(DFN1C0_14_Q), .CLK(RCLOCK), 
        .CLR(RESET), .Q(WGRYSYNC_3_net));
    DFN1C0 DFN1C0_RBIN_9_inst(.D(RBINNXT_9_net), .CLK(RCLOCK), 
        .CLR(RESET), .Q(RBIN_9_net));
    MX2 MX2_1(.A(RAM512X18_0_RD14), .B(RAM512X18_1_RD14), .S(
        DFN1_1_Q), .Y(MX2_1_Y));
    XNOR3 XNOR3_28(.A(RGRYSYNC_7_net), .B(RGRYSYNC_6_net), .C(
        RGRYSYNC_5_net), .Y(XNOR3_28_Y));
    OA1C OA1C_0(.A(RDIFF_9_net), .B(EMPTYVALUECONST_0_net), .C(
        RDIFF_10_net), .Y(OA1C_0_Y));
    OR2A OR2A_17(.A(WDIFF_2_net), .B(FULLCONSTVALUE_0_net), .Y(
        OR2A_17_Y));
    DFN1E1C0 DFN1E1C0_Q_6_inst(.D(QXI_6_net), .CLK(RCLOCK), .CLR(
        RESET), .E(DVLDI), .Q(Q[6]));
    AND2 AND2_96(.A(AND2_80_Y), .B(XOR2_108_Y), .Y(AND2_96_Y));
    AND3 AND3_8(.A(XNOR2_34_Y), .B(XNOR2_7_Y), .C(XNOR2_4_Y), .Y(
        AND3_8_Y));
    MX2 MX2_QXI_14_inst(.A(MX2_10_Y), .B(RAM512X18_2_RD15), .S(
        DFN1_0_Q), .Y(QXI_14_net));
    AO1 AO1_59(.A(XOR2_66_Y), .B(AO1_18_Y), .C(AND2_49_Y), .Y(
        AO1_59_Y));
    XOR2 XOR2_71(.A(WBINNXT_6_net), .B(INV_13_Y), .Y(XOR2_71_Y));
    MX2 MX2_QXI_9_inst(.A(MX2_5_Y), .B(RAM512X18_2_RD10), .S(
        DFN1_0_Q), .Y(QXI_9_net));
    XNOR2 XNOR2_28(.A(WRADDRGEN_CONST_0_net), .B(MEM_WADDR_5_net), 
        .Y(XNOR2_28_Y));
    AND2 AND2_18(.A(AND2_77_Y), .B(XOR2_11_Y), .Y(AND2_18_Y));
    XOR2 XOR2_96(.A(RBINNXT_6_net), .B(RBINNXT_7_net), .Y(
        XOR2_96_Y));
    AND2 AND2_78(.A(AND2_115_Y), .B(AND2_36_Y), .Y(AND2_78_Y));
    AO1 AO1_30(.A(XOR2_81_Y), .B(AND2_37_Y), .C(AND2_1_Y), .Y(
        AO1_30_Y));
    DFN1C0 DFN1C0_1(.D(RGRY_0_net), .CLK(WCLOCK), .CLR(RESET), .Q(
        DFN1C0_1_Q));
    XNOR2 XNOR2_4(.A(WRADDRGEN_CONST_8_net), .B(MEM_WADDR_8_net), 
        .Y(XNOR2_4_Y));
    AND2 AND2_40(.A(RBIN_0_net), .B(MEMORYRE), .Y(AND2_40_Y));
    DFN1C0 DFN1C0_WGRY_11_inst(.D(XOR2_46_Y), .CLK(WCLOCK), .CLR(
        RESET), .Q(WGRY_11_net));
    XNOR2 XNOR2_36(.A(WRADDRGEN_CONST_0_net), .B(MEM_WADDR_2_net), 
        .Y(XNOR2_36_Y));
    XOR2 XOR2_24(.A(RBIN_2_net), .B(GND), .Y(XOR2_24_Y));
    XOR2 XOR2_34(.A(WBINNXT_1_net), .B(WBINNXT_2_net), .Y(
        XOR2_34_Y));
    AND2 AND2_32(.A(AND2_114_Y), .B(XOR2_5_Y), .Y(AND2_32_Y));
    AO1C AO1C_3(.A(RDIFF_4_net), .B(EMPTYVALUECONST_0_net), .C(
        RDIFF_3_net), .Y(AO1C_3_Y));
    DFN1C0 DFN1C0_RBIN_5_inst(.D(RBINNXT_5_net), .CLK(RCLOCK), 
        .CLR(RESET), .Q(RBIN_5_net));
    XNOR3 XNOR3_34(.A(WGRYSYNC_5_net), .B(WGRYSYNC_4_net), .C(
        XNOR3_32_Y), .Y(XNOR3_34_Y));
    AND2 AND2_60(.A(XOR2_84_Y), .B(XOR2_43_Y), .Y(AND2_60_Y));
    XNOR3 XNOR3_2(.A(WGRYSYNC_8_net), .B(WGRYSYNC_7_net), .C(
        WGRYSYNC_6_net), .Y(XNOR3_2_Y));
    MX2 MX2_0(.A(RAM512X18_0_RD3), .B(RAM512X18_1_RD3), .S(
        DFN1_1_Q), .Y(MX2_0_Y));
    XOR2 XOR2_43(.A(WBINNXT_8_net), .B(INV_20_Y), .Y(XOR2_43_Y));
    DFN1C0 DFN1C0_10(.D(RGRY_7_net), .CLK(WCLOCK), .CLR(RESET), 
        .Q(DFN1C0_10_Q));
    XOR2 XOR2_WBINNXT_11_inst(.A(XOR2_26_Y), .B(AO1_7_Y), .Y(
        WBINNXT_11_net));
    XOR2 XOR2_RBINNXT_5_inst(.A(XOR2_78_Y), .B(AO1_31_Y), .Y(
        RBINNXT_5_net));
    XOR2 XOR2_61(.A(RBIN_8_net), .B(GND), .Y(XOR2_61_Y));
    AND2 AND2_85(.A(WBIN_9_net), .B(GND), .Y(AND2_85_Y));
    XNOR2 XNOR2_2(.A(WRADDRGEN_CONST_0_net), .B(MEM_WADDR_0_net), 
        .Y(XNOR2_2_Y));
    XOR2 XOR2_49(.A(RBIN_3_net), .B(GND), .Y(XOR2_49_Y));
    MX2 MX2_QXI_2_inst(.A(MX2_6_Y), .B(RAM512X18_2_RD2), .S(
        DFN1_0_Q), .Y(QXI_2_net));
    XOR2 XOR2_WDIFF_7_inst(.A(XOR2_101_Y), .B(AO1_61_Y), .Y(
        WDIFF_7_net));
    AO1 AO1_35(.A(AND2_17_Y), .B(AO1_13_Y), .C(AO1_57_Y), .Y(
        AO1_35_Y));
    AO1 AO1_27(.A(XOR2_25_Y), .B(AO1_44_Y), .C(AND2_31_Y), .Y(
        AO1_27_Y));
    INV WEBUBBLE(.A(WE), .Y(WEP));
    DFN1E1C0 DFN1E1C0_Q_11_inst(.D(QXI_11_net), .CLK(RCLOCK), 
        .CLR(RESET), .E(DVLDI), .Q(Q[11]));
    INV INV_14(.A(RBINNXT_5_net), .Y(INV_14_Y));
    AND2 AND2_53(.A(WBINSYNC_2_net), .B(INV_5_Y), .Y(AND2_53_Y));
    XOR3 XOR3_22(.A(MEM_WADDR_6_net), .B(GND), .C(MAJ3_14_Y), .Y(
        XOR3_22_Y));
    AO1 AO1_13(.A(AND2_56_Y), .B(AO1_40_Y), .C(AO1_4_Y), .Y(
        AO1_13_Y));
    MX2 MX2_14(.A(RAM512X18_0_RD7), .B(RAM512X18_1_RD7), .S(
        DFN1_1_Q), .Y(MX2_14_Y));
    XOR2 XOR2_WDIFF_10_inst(.A(XOR2_86_Y), .B(AO1_59_Y), .Y(
        WDIFF_10_net));
    XOR3 XOR3_8(.A(MEM_RADDR_4_net), .B(GND), .C(MAJ3_6_Y), .Y(
        XOR3_8_Y));
    DFN1E1C0 DFN1E1C0_Q_15_inst(.D(QXI_15_net), .CLK(RCLOCK), 
        .CLR(RESET), .E(DVLDI), .Q(Q[15]));
    AND2 AND2_99(.A(AND2_79_Y), .B(AND2_39_Y), .Y(AND2_99_Y));
    XOR2 XOR2_47(.A(WBINNXT_4_net), .B(INV_12_Y), .Y(XOR2_47_Y));
    XNOR3 XNOR3_16(.A(RGRYSYNC_7_net), .B(RGRYSYNC_6_net), .C(
        RGRYSYNC_5_net), .Y(XNOR3_16_Y));
    AO1 AO1_28(.A(XOR2_100_Y), .B(AO1_17_Y), .C(AND2_52_Y), .Y(
        AO1_28_Y));
    XOR2 XOR2_9(.A(RBIN_8_net), .B(GND), .Y(XOR2_9_Y));
    DFN1C0 DFN1C0_RGRY_2_inst(.D(XOR2_97_Y), .CLK(RCLOCK), .CLR(
        RESET), .Q(RGRY_2_net));
    AO1 AO1_12(.A(AND2_36_Y), .B(AO1_44_Y), .C(AO1_16_Y), .Y(
        AO1_12_Y));
    XOR2 XOR2_25(.A(WBIN_2_net), .B(GND), .Y(XOR2_25_Y));
    INV INV_12(.A(RBINSYNC_3_net), .Y(INV_12_Y));
    DFN1C0 DFN1C0_RGRYSYNC_4_inst(.D(DFN1C0_3_Q), .CLK(WCLOCK), 
        .CLR(RESET), .Q(RGRYSYNC_4_net));
    XOR2 XOR2_35(.A(WBINSYNC_7_net), .B(INV_17_Y), .Y(XOR2_35_Y));
    AND3 AND3_0(.A(AND3_8_Y), .B(AND3_12_Y), .C(AND3_9_Y), .Y(
        AND3_0_Y));
    XNOR3 XNOR3_6(.A(RGRYSYNC_4_net), .B(RGRYSYNC_3_net), .C(
        RGRYSYNC_2_net), .Y(XNOR3_6_Y));
    XOR3 XOR3_26(.A(MEM_WADDR_9_net), .B(GND), .C(MAJ3_8_Y), .Y(
        XOR3_26_Y));
    XOR2 XOR2_RBINNXT_2_inst(.A(XOR2_94_Y), .B(AO1_14_Y), .Y(
        RBINNXT_2_net));
    MX2 MX2_7(.A(RAM512X18_0_RD9), .B(RAM512X18_1_RD9), .S(
        DFN1_1_Q), .Y(MX2_7_Y));
    AND2 AND2_17(.A(XOR2_75_Y), .B(XOR2_35_Y), .Y(AND2_17_Y));
    AND2 AND2_114(.A(AND2_84_Y), .B(AND2_17_Y), .Y(AND2_114_Y));
    AND2 AND2_77(.A(AND2_9_Y), .B(AND2_5_Y), .Y(AND2_77_Y));
    AO1 AO1_3(.A(AND2_95_Y), .B(NAND3A_8_Y), .C(NOR3_0_Y), .Y(
        AO1_3_Y));
    AND3 AND3_7(.A(XNOR2_17_Y), .B(XNOR2_6_Y), .C(XNOR2_35_Y), .Y(
        AND3_7_Y));
    AND2 AND2_38(.A(AND2_33_Y), .B(XOR2_70_Y), .Y(AND2_38_Y));
    OR3 OR3_0(.A(AND2_29_Y), .B(AND2_59_Y), .C(AND2_107_Y), .Y(
        OR3_0_Y));
    MX2 MX2_6(.A(RAM512X18_0_RD2), .B(RAM512X18_1_RD2), .S(
        DFN1_1_Q), .Y(MX2_6_Y));
    DFN1C0 DFN1C0_RGRYSYNC_8_inst(.D(DFN1C0_18_Q), .CLK(WCLOCK), 
        .CLR(RESET), .Q(RGRYSYNC_8_net));
    XOR2 XOR2_72(.A(WBINNXT_2_net), .B(INV_1_Y), .Y(XOR2_72_Y));
    XOR2 XOR2_WDIFF_5_inst(.A(XOR2_63_Y), .B(AO1_37_Y), .Y(
        WDIFF_5_net));
    AO1 AO1_56(.A(XOR2_50_Y), .B(AO1_37_Y), .C(AND2_110_Y), .Y(
        AO1_56_Y));
    AO1 AO1_0(.A(XOR2_9_Y), .B(AO1_8_Y), .C(AND2_55_Y), .Y(
        AO1_0_Y));
    AND2 AND2_111(.A(AND2_27_Y), .B(XOR2_69_Y), .Y(AND2_111_Y));
    NAND3A NAND3A_9(.A(NOR3A_1_Y), .B(OR2A_8_Y), .C(NAND3A_11_Y), 
        .Y(NAND3A_9_Y));
    DFN1C0 DFN1C0_WGRY_9_inst(.D(XOR2_39_Y), .CLK(WCLOCK), .CLR(
        RESET), .Q(WGRY_9_net));
    DFN1P0 DFN1P0_EMPTY(.D(AOI1_0_Y), .CLK(RCLOCK), .PRE(RESET), 
        .Q(EMPTY));
    DFN1E1C0 DFN1E1C0_MEM_WADDR_11_inst(.D(XOR3_19_Y), .CLK(
        WCLOCK), .CLR(AND2_98_Y), .E(AND2A_3_Y), .Q(
        MEM_WADDR_11_net));
    AND2 AND2_83(.A(RBIN_3_net), .B(GND), .Y(AND2_83_Y));
    AO1C AO1C_5(.A(FULLCONSTVALUE_0_net), .B(WDIFF_1_net), .C(
        FULLCONSTVALUE_0_net), .Y(AO1C_5_Y));
    OR2A OR2A_4(.A(FULLCONSTVALUE_8_net), .B(WDIFF_8_net), .Y(
        OR2A_4_Y));
    MX2 MX2_QXI_5_inst(.A(MX2_3_Y), .B(RAM512X18_2_RD5), .S(
        DFN1_0_Q), .Y(QXI_5_net));
    DFN1E1C0 DFN1E1C0_Q_13_inst(.D(QXI_13_net), .CLK(RCLOCK), 
        .CLR(RESET), .E(DVLDI), .Q(Q[13]));
    OR2A OR2A_11(.A(MEM_RADDR_9_net), .B(MEM_RADDR_8_net), .Y(
        OR2A_11_Y));
    AND2 AND2_90(.A(AND2_48_Y), .B(XOR2_84_Y), .Y(AND2_90_Y));
    AND2 AND2_11(.A(RBIN_2_net), .B(GND), .Y(AND2_11_Y));
    XOR2 XOR2_18(.A(WBIN_0_net), .B(MEMORYWE), .Y(XOR2_18_Y));
    DFN1E1C0 DFN1E1C0_MEM_RADDR_2_inst(.D(XOR3_21_Y), .CLK(RCLOCK)
        , .CLR(AND2_41_Y), .E(AND2A_1_Y), .Q(MEM_RADDR_2_net));
    AND2 AND2_71(.A(AND2_4_Y), .B(AND2_79_Y), .Y(AND2_71_Y));
    XOR2 XOR2_20(.A(WBIN_11_net), .B(GND), .Y(XOR2_20_Y));
    AOI1 AOI1_1(.A(AND3_5_Y), .B(AO1_26_Y), .C(AO1_64_Y), .Y(
        AOI1_1_Y));
    XOR2 XOR2_76(.A(WBINSYNC_8_net), .B(INV_2_Y), .Y(XOR2_76_Y));
    DFN1E1C0 DFN1E1C0_MEM_RADDR_6_inst(.D(XOR3_15_Y), .CLK(RCLOCK)
        , .CLR(AND2_41_Y), .E(AND2A_1_Y), .Q(MEM_RADDR_6_net));
    XOR2 XOR2_30(.A(RBINNXT_1_net), .B(RBINNXT_2_net), .Y(
        XOR2_30_Y));
    XOR2 XOR2_RDIFF_7_inst(.A(XOR2_76_Y), .B(AO1_35_Y), .Y(
        RDIFF_7_net));
    XOR2 XOR2_88(.A(RBINNXT_4_net), .B(RBINNXT_5_net), .Y(
        XOR2_88_Y));
    DFN1C0 DFN1C0_13(.D(WGRY_2_net), .CLK(RCLOCK), .CLR(RESET), 
        .Q(DFN1C0_13_Q));
    XNOR3 XNOR3_3(.A(WGRYSYNC_11_net), .B(WGRYSYNC_10_net), .C(
        WGRYSYNC_9_net), .Y(XNOR3_3_Y));
    DFN1E1C0 DFN1E1C0_MEM_WADDR_0_inst(.D(XOR2_85_Y), .CLK(WCLOCK)
        , .CLR(AND2_98_Y), .E(AND2A_3_Y), .Q(MEM_WADDR_0_net));
    INV INV_8(.A(AND3_13_Y), .Y(INV_8_Y));
    MX2 MX2_QXI_10_inst(.A(MX2_4_Y), .B(RAM512X18_2_RD11), .S(
        DFN1_0_Q), .Y(QXI_10_net));
    NAND3A NAND3A_6(.A(WDIFF_1_net), .B(FULLCONSTVALUE_0_net), .C(
        OR2A_17_Y), .Y(NAND3A_6_Y));
    XOR2 XOR2_62(.A(WBIN_3_net), .B(GND), .Y(XOR2_62_Y));
    DFN1C0 DFN1C0_WGRYSYNC_11_inst(.D(DFN1C0_21_Q), .CLK(RCLOCK), 
        .CLR(RESET), .Q(WGRYSYNC_11_net));
    DFN1 DFN1_3(.D(MEM_WADDR_9_net), .CLK(WCLOCK), .Q(DFN1_3_Q));
    AND2 AND2_4(.A(AND2_78_Y), .B(AND2_88_Y), .Y(AND2_4_Y));
    XOR3 XOR3_2(.A(MEM_WADDR_10_net), .B(GND), .C(MAJ3_17_Y), .Y(
        XOR3_2_Y));
    AND2 AND2_0(.A(RBIN_7_net), .B(GND), .Y(AND2_0_Y));
    XNOR2 XNOR2_40(.A(RDIFF_10_net), .B(EMPTYVALUECONST_0_net), 
        .Y(XNOR2_40_Y));
    DFN1C0 DFN1C0_WBIN_7_inst(.D(WBINNXT_7_net), .CLK(WCLOCK), 
        .CLR(RESET), .Q(WBIN_7_net));
    AO1 AO1_34(.A(XOR2_65_Y), .B(AND2_7_Y), .C(AND2_101_Y), .Y(
        AO1_34_Y));
    XOR3 XOR3_3(.A(MEM_RADDR_1_net), .B(GND), .C(AND2_63_Y), .Y(
        XOR3_3_Y));
    DFN1E1C0 DFN1E1C0_MEM_WADDR_3_inst(.D(XOR3_17_Y), .CLK(WCLOCK)
        , .CLR(AND2_98_Y), .E(AND2A_3_Y), .Q(MEM_WADDR_3_net));
    DFN1C0 DFN1C0_RGRYSYNC_3_inst(.D(DFN1C0_8_Q), .CLK(WCLOCK), 
        .CLR(RESET), .Q(RGRYSYNC_3_net));
    XNOR2 XNOR2_33(.A(EMPTYVALUECONST_0_net), .B(RDIFF_10_net), 
        .Y(XNOR2_33_Y));
    AO1 AO1_43(.A(AND2_5_Y), .B(AO1_14_Y), .C(AO1_23_Y), .Y(
        AO1_43_Y));
    AND2 AND2_16(.A(AND2_80_Y), .B(AND2_24_Y), .Y(AND2_16_Y));
    AND2 AND2_76(.A(AND2_78_Y), .B(XOR2_6_Y), .Y(AND2_76_Y));
    DFN1C0 DFN1C0_DVLDI(.D(AND2A_2_Y), .CLK(RCLOCK), .CLR(RESET), 
        .Q(DVLDI));
    MX2 MX2_10(.A(RAM512X18_0_RD15), .B(RAM512X18_1_RD15), .S(
        DFN1_1_Q), .Y(MX2_10_Y));
    AND2 AND2_6(.A(WBIN_0_net), .B(MEMORYWE), .Y(AND2_6_Y));
    AO1 AO1_17(.A(AND2_97_Y), .B(AO1_13_Y), .C(AO1_54_Y), .Y(
        AO1_17_Y));
    MX2 MX2_QXI_7_inst(.A(MX2_14_Y), .B(RAM512X18_2_RD7), .S(
        DFN1_0_Q), .Y(QXI_7_net));