📄 soft_fifo1280x8.v
字号:
`timescale 1 ns/100 ps
// Version: 8.0 8.0.0.40
module soft_fifo1280x8(DATA,Q,WE,RE,WCLOCK,RCLOCK,FULL,EMPTY,
RESET);
input [7:0] DATA;
output [15:0] Q;
input WE, RE, WCLOCK, RCLOCK;
output FULL, EMPTY;
input RESET;
wire WEP, REP, WBIN_0_net, WBIN_1_net, WBIN_2_net, WBIN_3_net,
WBIN_4_net, WBIN_5_net, WBIN_6_net, WBIN_7_net,
WBIN_8_net, WBIN_9_net, WBIN_10_net, WBIN_11_net,
WBINNXT_0_net, WBINNXT_1_net, WBINNXT_2_net,
WBINNXT_3_net, WBINNXT_4_net, WBINNXT_5_net,
WBINNXT_6_net, WBINNXT_7_net, WBINNXT_8_net,
WBINNXT_9_net, WBINNXT_10_net, WBINNXT_11_net,
RBINSYNC_0_net, RBINSYNC_1_net, RBINSYNC_2_net,
RBINSYNC_3_net, RBINSYNC_4_net, RBINSYNC_5_net,
RBINSYNC_6_net, RBINSYNC_7_net, RBINSYNC_8_net,
RBINSYNC_9_net, RBINSYNC_10_net, RBINSYNCSHIFT_0_net,
RBIN_0_net, RBIN_1_net, RBIN_2_net, RBIN_3_net,
RBIN_4_net, RBIN_5_net, RBIN_6_net, RBIN_7_net,
RBIN_8_net, RBIN_9_net, RBIN_10_net, RBINNXT_0_net,
RBINNXT_1_net, RBINNXT_2_net, RBINNXT_3_net,
RBINNXT_4_net, RBINNXT_5_net, RBINNXT_6_net,
RBINNXT_7_net, RBINNXT_8_net, RBINNXT_9_net,
RBINNXT_10_net, WBINSYNC_0_net, WBINSYNC_1_net,
WBINSYNC_2_net, WBINSYNC_3_net, WBINSYNC_4_net,
WBINSYNC_5_net, WBINSYNC_6_net, WBINSYNC_7_net,
WBINSYNC_8_net, WBINSYNC_9_net, WBINSYNC_10_net,
WBINSYNC_11_net;
wire FULLCONSTVALUE_0_net = RBINSYNCSHIFT_0_net;
wire FULLCONSTVALUE_8_net, WDIFF_0_net, WDIFF_1_net,
WDIFF_2_net, WDIFF_3_net, WDIFF_4_net, WDIFF_5_net,
WDIFF_6_net, WDIFF_7_net, WDIFF_8_net, WDIFF_9_net,
WDIFF_10_net, WDIFF_11_net, MEMORYWE, MEMWENEG,
WGRY_0_net, WGRY_1_net, WGRY_2_net, WGRY_3_net,
WGRY_4_net, WGRY_5_net, WGRY_6_net, WGRY_7_net,
WGRY_8_net, WGRY_9_net, WGRY_10_net, WGRY_11_net,
RGRYSYNC_0_net, RGRYSYNC_1_net, RGRYSYNC_2_net,
RGRYSYNC_3_net, RGRYSYNC_4_net, RGRYSYNC_5_net,
RGRYSYNC_6_net, RGRYSYNC_7_net, RGRYSYNC_8_net,
RGRYSYNC_9_net, RGRYSYNC_10_net;
wire EMPTYVALUECONST_0_net = RBINSYNCSHIFT_0_net;
wire RDIFF_0_net, RDIFF_1_net, RDIFF_2_net, RDIFF_3_net,
RDIFF_4_net, RDIFF_5_net, RDIFF_6_net, RDIFF_7_net,
RDIFF_8_net, RDIFF_9_net, RDIFF_10_net, MEMORYRE,
MEMRENEG, DVLDI, DVLDX, RGRY_0_net, RGRY_1_net,
RGRY_2_net, RGRY_3_net, RGRY_4_net, RGRY_5_net,
RGRY_6_net, RGRY_7_net, RGRY_8_net, RGRY_9_net,
RGRY_10_net, WGRYSYNC_0_net, WGRYSYNC_1_net,
WGRYSYNC_2_net, WGRYSYNC_3_net, WGRYSYNC_4_net,
WGRYSYNC_5_net, WGRYSYNC_6_net, WGRYSYNC_7_net,
WGRYSYNC_8_net, WGRYSYNC_9_net, WGRYSYNC_10_net,
WGRYSYNC_11_net, QXI_0_net, QXI_1_net, QXI_2_net,
QXI_3_net, QXI_4_net, QXI_5_net, QXI_6_net, QXI_7_net,
QXI_8_net, QXI_9_net, QXI_10_net, QXI_11_net, QXI_12_net,
QXI_13_net, QXI_14_net, QXI_15_net, MEM_WADDR_0_net,
MEM_WADDR_1_net, MEM_WADDR_2_net, MEM_WADDR_3_net,
MEM_WADDR_4_net, MEM_WADDR_5_net, MEM_WADDR_6_net,
MEM_WADDR_7_net, MEM_WADDR_8_net, MEM_WADDR_9_net,
MEM_WADDR_10_net, MEM_WADDR_11_net, MEM_RADDR_0_net,
MEM_RADDR_1_net, MEM_RADDR_2_net, MEM_RADDR_3_net,
MEM_RADDR_4_net, MEM_RADDR_5_net, MEM_RADDR_6_net,
MEM_RADDR_7_net, MEM_RADDR_8_net, MEM_RADDR_9_net,
MEM_RADDR_10_net, DFN1_3_Q, DFN1_2_Q, DFN1_1_Q, DFN1_0_Q,
OR2_5_Y, OR2A_2_Y, OR2A_10_Y, OR2_6_Y, OR2A_9_Y,
OR2A_11_Y, OR2_7_Y, OR2_1_Y, OR2_0_Y, OR2_2_Y, OR2_3_Y,
OR2_4_Y, RAM512X18_0_RD0, RAM512X18_0_RD1,
RAM512X18_0_RD2, RAM512X18_0_RD3, RAM512X18_0_RD4,
RAM512X18_0_RD5, RAM512X18_0_RD6, RAM512X18_0_RD7,
RAM512X18_1_RD0, RAM512X18_1_RD1, RAM512X18_1_RD2,
RAM512X18_1_RD3, RAM512X18_1_RD4, RAM512X18_1_RD5,
RAM512X18_1_RD6, RAM512X18_1_RD7, RAM512X18_2_RD0,
RAM512X18_2_RD1, RAM512X18_2_RD2, RAM512X18_2_RD3,
RAM512X18_2_RD4, RAM512X18_2_RD5, RAM512X18_2_RD6,
RAM512X18_2_RD7, RAM512X18_0_RD9, RAM512X18_0_RD10,
RAM512X18_0_RD11, RAM512X18_0_RD12, RAM512X18_0_RD13,
RAM512X18_0_RD14, RAM512X18_0_RD15, RAM512X18_0_RD16,
RAM512X18_1_RD9, RAM512X18_1_RD10, RAM512X18_1_RD11,
RAM512X18_1_RD12, RAM512X18_1_RD13, RAM512X18_1_RD14,
RAM512X18_1_RD15, RAM512X18_1_RD16, RAM512X18_2_RD9,
RAM512X18_2_RD10, RAM512X18_2_RD11, RAM512X18_2_RD12,
RAM512X18_2_RD13, RAM512X18_2_RD14, RAM512X18_2_RD15,
RAM512X18_2_RD16, MX2_2_Y, MX2_12_Y, MX2_0_Y, MX2_14_Y,
MX2_3_Y, MX2_6_Y, MX2_9_Y, MX2_8_Y, MX2_15_Y, MX2_10_Y,
MX2_13_Y, MX2_11_Y, MX2_1_Y, MX2_4_Y, MX2_7_Y, MX2_5_Y,
NAND2_1_Y, DFN1C0_19_Q, DFN1C0_11_Q, DFN1C0_13_Q,
DFN1C0_14_Q, DFN1C0_0_Q, DFN1C0_17_Q, DFN1C0_6_Q,
DFN1C0_4_Q, DFN1C0_7_Q, DFN1C0_9_Q, DFN1C0_2_Q,
DFN1C0_21_Q, XNOR3_35_Y, XOR3_1_Y, XNOR3_2_Y, XNOR3_19_Y,
XOR3_11_Y, XNOR3_12_Y, XNOR3_26_Y, XNOR3_18_Y, XOR3_25_Y,
XNOR3_30_Y, XNOR3_21_Y, XNOR3_32_Y, XNOR3_34_Y,
XNOR3_13_Y, XNOR3_15_Y, XNOR3_14_Y, XNOR3_10_Y,
XNOR3_20_Y, XNOR3_33_Y, XNOR3_7_Y, XNOR3_22_Y, XNOR3_29_Y,
XOR3_10_Y, XNOR3_24_Y, XNOR3_3_Y, DFN1C0_1_Q, DFN1C0_20_Q,
DFN1C0_12_Q, DFN1C0_8_Q, DFN1C0_3_Q, DFN1C0_16_Q,
DFN1C0_22_Q, DFN1C0_10_Q, DFN1C0_18_Q, DFN1C0_15_Q,
DFN1C0_5_Q;
wire RDADDRGEN_CONST_0_net = RBINSYNCSHIFT_0_net;
wire RDADDRGEN_CONST_7_net = FULLCONSTVALUE_8_net;
wire XOR2_36_Y, XOR3_3_Y, XOR3_21_Y, XOR3_20_Y, XOR3_8_Y,
XOR3_14_Y, XOR3_15_Y, XOR3_27_Y, XOR3_24_Y, XOR3_16_Y,
XOR3_9_Y, AND2A_1_Y, AND2_41_Y, AND3_2_Y, INV_7_Y,
AND2_63_Y, MAJ3_9_Y, MAJ3_5_Y, MAJ3_6_Y, MAJ3_4_Y,
MAJ3_13_Y, MAJ3_3_Y, MAJ3_2_Y, MAJ3_0_Y, MAJ3_12_Y,
XNOR2_3_Y, XNOR2_41_Y, XNOR2_24_Y, XNOR2_16_Y, XNOR2_31_Y,
XNOR2_21_Y, XNOR2_17_Y, XNOR2_6_Y, XNOR2_35_Y, XNOR2_20_Y,
XNOR2_14_Y, AND3_16_Y, AND3_4_Y, AND3_7_Y, AND3_6_Y,
NOR2A_0_Y, INV_5_Y, INV_3_Y, INV_24_Y, INV_16_Y, INV_14_Y,
INV_17_Y, INV_2_Y, INV_22_Y, INV_21_Y, INV_15_Y, INV_6_Y,
AND2_53_Y, AND2_89_Y, AND2_10_Y, AND2_43_Y, AND2_54_Y,
AND2_93_Y, AND2_22_Y, AND2_51_Y, AND2_7_Y, AND2_101_Y,
AND2_52_Y, AND2_87_Y, XOR2_4_Y, XOR2_92_Y, XOR2_17_Y,
XOR2_73_Y, XOR2_75_Y, XOR2_35_Y, XOR2_5_Y, XOR2_65_Y,
XOR2_100_Y, XOR2_77_Y, AND2_19_Y, AO1_4_Y, AND2_56_Y,
AO1_57_Y, AND2_17_Y, AO1_34_Y, AND2_94_Y, AO1_25_Y,
AND2_69_Y, AND2_84_Y, AO1_54_Y, AND2_97_Y, AND2_108_Y,
AND2_114_Y, AO1_15_Y, AND2_61_Y, AND2_34_Y, AND2_64_Y,
AND2_32_Y, AND2_112_Y, OR3_1_Y, AO1_40_Y, AO1_38_Y,
AO1_13_Y, AO1_21_Y, AO1_35_Y, AO1_29_Y, AO1_17_Y,
AO1_28_Y, XOR2_31_Y, XOR2_59_Y, XOR2_15_Y, XOR2_93_Y,
XOR2_89_Y, XOR2_45_Y, XOR2_76_Y, XOR2_29_Y, XOR2_7_Y,
XOR2_2_Y;
wire WRADDRGEN_CONST_0_net = RBINSYNCSHIFT_0_net;
wire WRADDRGEN_CONST_8_net = FULLCONSTVALUE_8_net;
wire XOR2_85_Y, XOR3_6_Y, XOR3_18_Y, XOR3_17_Y, XOR3_13_Y,
XOR3_5_Y, XOR3_22_Y, XOR3_0_Y, XOR3_28_Y, XOR3_26_Y,
XOR3_2_Y, XOR3_19_Y, AND2A_3_Y, AND2_98_Y, AND3_13_Y,
INV_8_Y, AND2_25_Y, MAJ3_18_Y, MAJ3_1_Y, MAJ3_11_Y,
MAJ3_16_Y, MAJ3_14_Y, MAJ3_10_Y, MAJ3_7_Y, MAJ3_8_Y,
MAJ3_17_Y, MAJ3_15_Y, XNOR2_2_Y, XNOR2_37_Y, XNOR2_36_Y,
XNOR2_8_Y, XNOR2_42_Y, XNOR2_28_Y, XNOR2_34_Y, XNOR2_7_Y,
XNOR2_4_Y, XNOR2_30_Y, XNOR2_1_Y, XNOR2_27_Y, AND3_12_Y,
AND3_0_Y, AND2_73_Y, AND3_8_Y, AND3_9_Y, XOR2_28_Y,
XOR2_34_Y, XOR2_33_Y, XOR2_1_Y, XOR2_52_Y, XOR2_41_Y,
XOR2_95_Y, XOR2_99_Y, XOR2_0_Y, XOR2_39_Y, XOR2_8_Y,
XOR2_46_Y, AND2_67_Y, AND2_31_Y, AND2_45_Y, AND2_102_Y,
AND2_72_Y, AND2_109_Y, AND2_91_Y, AND2_26_Y, AND2_85_Y,
AND2_66_Y, AND2_116_Y, XOR2_18_Y, XOR2_48_Y, XOR2_25_Y,
XOR2_68_Y, XOR2_6_Y, XOR2_55_Y, XOR2_70_Y, XOR2_44_Y,
XOR2_79_Y, XOR2_21_Y, XOR2_40_Y, XOR2_20_Y, AND2_115_Y,
AO1_16_Y, AND2_36_Y, AO1_41_Y, AND2_74_Y, AO1_33_Y,
AND2_50_Y, AO1_52_Y, AND2_79_Y, AO1_51_Y, AND2_39_Y,
AND2_78_Y, AO1_39_Y, AND2_88_Y, AO1_1_Y, AND2_99_Y,
AND2_4_Y, AO1_22_Y, AND2_113_Y, AND2_33_Y, AND2_71_Y,
AND2_47_Y, AND2_76_Y, AND2_38_Y, AND2_75_Y, AND2_86_Y,
AND2_6_Y, AO1_44_Y, AO1_27_Y, AO1_12_Y, AO1_32_Y,
AO1_58_Y, AO1_9_Y, AO1_46_Y, AO1_63_Y, AO1_11_Y, AO1_7_Y,
XOR2_90_Y, XOR2_19_Y, XOR2_62_Y, XOR2_32_Y, XOR2_106_Y,
XOR2_58_Y, XOR2_103_Y, XOR2_37_Y, XOR2_14_Y, XOR2_56_Y,
XOR2_26_Y, AND2A_2_Y, XOR2_109_Y, XOR2_30_Y, XOR2_97_Y,
XOR2_104_Y, XOR2_88_Y, XOR2_105_Y, XOR2_96_Y, XOR2_22_Y,
XOR2_80_Y, XOR2_57_Y, XOR2_110_Y, AND2_46_Y, AND2_11_Y,
AND2_83_Y, AND2_37_Y, AND2_1_Y, AND2_58_Y, AND2_0_Y,
AND2_55_Y, AND2_14_Y, AND2_106_Y, XOR2_67_Y, XOR2_102_Y,
XOR2_24_Y, XOR2_49_Y, XOR2_11_Y, XOR2_81_Y, XOR2_60_Y,
XOR2_42_Y, XOR2_9_Y, XOR2_83_Y, XOR2_69_Y, AND2_9_Y,
AO1_23_Y, AND2_5_Y, AO1_30_Y, AND2_81_Y, AO1_55_Y,
AND2_2_Y, AO1_20_Y, AND2_104_Y, AND2_77_Y, AO1_2_Y,
AND2_8_Y, AND2_35_Y, AND2_57_Y, AND2_27_Y, AND2_23_Y,
AND2_18_Y, AND2_92_Y, AND2_15_Y, AO1_45_Y, AND2_111_Y,
AND2_40_Y, AO1_14_Y, AO1_50_Y, AO1_43_Y, AO1_31_Y,
AO1_49_Y, AO1_62_Y, AO1_8_Y, AO1_0_Y, AO1_48_Y, XOR2_3_Y,
XOR2_94_Y, XOR2_51_Y, XOR2_74_Y, XOR2_78_Y, XOR2_10_Y,
XOR2_107_Y, XOR2_61_Y, XOR2_87_Y, XOR2_13_Y, NAND2_0_Y,
NOR2A_1_Y, INV_4_Y, INV_1_Y, INV_23_Y, INV_12_Y, INV_11_Y,
INV_13_Y, INV_0_Y, INV_20_Y, INV_19_Y, INV_18_Y, INV_10_Y,
INV_9_Y, AND2_29_Y, AND2_59_Y, AND2_107_Y, AND2_20_Y,
AND2_30_Y, AND2_62_Y, AND2_110_Y, AND2_28_Y, AND2_100_Y,
AND2_70_Y, AND2_49_Y, AND2_21_Y, AND2_42_Y, XOR2_82_Y,
XOR2_64_Y, XOR2_108_Y, XOR2_47_Y, XOR2_50_Y, XOR2_16_Y,
XOR2_84_Y, XOR2_43_Y, XOR2_66_Y, XOR2_54_Y, XOR2_27_Y,
AND2_80_Y, AO1_36_Y, AND2_24_Y, AO1_47_Y, AND2_68_Y,
AO1_19_Y, AND2_60_Y, AO1_65_Y, AND2_105_Y, AND2_16_Y,
AO1_53_Y, AND2_12_Y, AND2_13_Y, AND2_48_Y, AND2_103_Y,
AND2_96_Y, AND2_44_Y, AND2_90_Y, AND2_82_Y, AO1_42_Y,
AND2_3_Y, OR3_0_Y, AO1_10_Y, AO1_5_Y, AO1_37_Y, AO1_56_Y,
AO1_61_Y, AO1_60_Y, AO1_18_Y, AO1_59_Y, AO1_6_Y,
XOR2_53_Y, XOR2_72_Y, XOR2_23_Y, XOR2_98_Y, XOR2_63_Y,
XOR2_71_Y, XOR2_101_Y, XOR2_38_Y, XOR2_12_Y, XOR2_86_Y,
XOR2_91_Y, AOI1_1_Y, AND3_5_Y, AO1_64_Y, AO1_26_Y,
AND3_1_Y, NAND3A_9_Y, NAND3A_2_Y, OR2A_6_Y, AO1C_2_Y,
NOR3A_1_Y, OR2A_8_Y, NAND3A_11_Y, XNOR2_26_Y, XNOR2_23_Y,
XNOR2_19_Y, OR2A_3_Y, AO1C_4_Y, NOR3A_6_Y, OR2A_4_Y,
NAND3A_12_Y, XNOR2_15_Y, XNOR2_0_Y, XNOR2_12_Y,
XNOR2_44_Y, XNOR2_11_Y, XNOR2_22_Y, AND3_14_Y, AND2_65_Y,
AND3_3_Y, NAND3A_7_Y, NAND3A_5_Y, OR2A_7_Y, AO1C_6_Y,
NOR3A_4_Y, OR2A_14_Y, NAND3A_0_Y, XNOR2_13_Y, XNOR2_9_Y,
XNOR2_5_Y, OR2A_17_Y, AO1C_5_Y, NOR3A_5_Y, OR2A_15_Y,
NAND3A_6_Y, XNOR3_28_Y, XOR3_12_Y, XNOR3_31_Y, XNOR3_9_Y,
XNOR3_36_Y, XNOR3_16_Y, XNOR3_8_Y, XOR3_7_Y, XNOR3_25_Y,
XNOR3_11_Y, XOR3_23_Y, XNOR3_4_Y, XNOR3_6_Y, XOR3_4_Y,
XNOR3_5_Y, XNOR3_27_Y, XNOR3_17_Y, XNOR3_1_Y, XNOR3_23_Y,
XNOR3_0_Y, AOI1_0_Y, AND3_10_Y, AO1_3_Y, AO1_24_Y,
AND2_95_Y, NOR3_0_Y, NAND3A_8_Y, OA1A_0_Y, AND2A_0_Y,
OA1C_0_Y, XNOR2_38_Y, XNOR2_33_Y, OR2A_1_Y, AO1C_0_Y,
NOR3A_2_Y, OR2A_13_Y, NAND3A_3_Y, XNOR2_32_Y, XNOR2_10_Y,
XNOR2_43_Y, XNOR2_18_Y, XNOR2_40_Y, AND3_11_Y, AND3_15_Y,
NAND3A_4_Y, NAND3A_10_Y, OR2A_12_Y, AO1C_3_Y, NOR3A_0_Y,
OR2A_0_Y, NAND3A_1_Y, XNOR2_29_Y, XNOR2_25_Y, XNOR2_39_Y,
OR2A_16_Y, AO1C_1_Y, NOR3A_3_Y, OR2A_5_Y, NAND3A_13_Y;
wire VCC = FULLCONSTVALUE_8_net;
wire GND = RBINSYNCSHIFT_0_net;
VCC VCC_1_net(.Y(FULLCONSTVALUE_8_net));
GND GND_1_net(.Y(RBINSYNCSHIFT_0_net));
DFN1C0 DFN1C0_WGRYSYNC_8_inst(.D(DFN1C0_7_Q), .CLK(RCLOCK),
.CLR(RESET), .Q(WGRYSYNC_8_net));
XOR2 XOR2_WDIFF_11_inst(.A(XOR2_91_Y), .B(AO1_6_Y), .Y(
WDIFF_11_net));
XNOR2 XNOR2_35(.A(RDADDRGEN_CONST_0_net), .B(MEM_RADDR_8_net),
.Y(XNOR2_35_Y));
AND2 AND2_12(.A(AND2_68_Y), .B(AND2_60_Y), .Y(AND2_12_Y));
AO1 AO1_23(.A(XOR2_49_Y), .B(AND2_11_Y), .C(AND2_83_Y), .Y(
AO1_23_Y));
MAJ3 MAJ3_9(.A(AND2_63_Y), .B(MEM_RADDR_1_net), .C(GND), .Y(
MAJ3_9_Y));
AND2 AND2_72(.A(WBIN_5_net), .B(GND), .Y(AND2_72_Y));
XNOR2 XNOR2_24(.A(RDADDRGEN_CONST_0_net), .B(MEM_RADDR_2_net),
.Y(XNOR2_24_Y));
MAJ3 MAJ3_17(.A(MAJ3_8_Y), .B(MEM_WADDR_9_net), .C(GND), .Y(
MAJ3_17_Y));
XNOR2 XNOR2_19(.A(WDIFF_11_net), .B(FULLCONSTVALUE_0_net), .Y(
XNOR2_19_Y));
DFN1C0 DFN1C0_RGRY_6_inst(.D(XOR2_96_Y), .CLK(RCLOCK), .CLR(
RESET), .Q(RGRY_6_net));
XNOR3 XNOR3_RBINSYNC_6_inst(.A(RGRYSYNC_7_net), .B(
RGRYSYNC_6_net), .C(XNOR3_23_Y), .Y(RBINSYNC_6_net));
XOR2 XOR2_58(.A(WBIN_6_net), .B(GND), .Y(XOR2_58_Y));
DFN1C0 DFN1C0_RGRY_7_inst(.D(XOR2_22_Y), .CLK(RCLOCK), .CLR(
RESET), .Q(RGRY_7_net));
XOR3 XOR3_21(.A(MEM_RADDR_2_net), .B(GND), .C(MAJ3_9_Y), .Y(
XOR3_21_Y));
XOR2 XOR2_RBINNXT_7_inst(.A(XOR2_107_Y), .B(AO1_62_Y), .Y(
RBINNXT_7_net));
DFN1C0 DFN1C0_22(.D(RGRY_6_net), .CLK(WCLOCK), .CLR(RESET),
.Q(DFN1C0_22_Q));
DFN1C0 DFN1C0_WGRY_2_inst(.D(XOR2_33_Y), .CLK(WCLOCK), .CLR(
RESET), .Q(WGRY_2_net));
AND2 AND2_49(.A(WBINNXT_9_net), .B(INV_19_Y), .Y(AND2_49_Y));
AND2 AND2_23(.A(AND2_9_Y), .B(XOR2_24_Y), .Y(AND2_23_Y));
XOR3 XOR3_7(.A(RGRYSYNC_10_net), .B(RGRYSYNC_9_net), .C(
RGRYSYNC_8_net), .Y(XOR3_7_Y));
XOR3 XOR3_18(.A(MEM_WADDR_2_net), .B(GND), .C(MAJ3_18_Y), .Y(
XOR3_18_Y));
AO1 AO1_22(.A(AND2_99_Y), .B(AO1_46_Y), .C(AO1_1_Y), .Y(
AO1_22_Y));
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