soft_fifo1280x8.gen

cmos数据到fifo再到usb的fifo部分程序(68013a)

Version:8.0.0.40
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_SOFTFIFO
LPM_HINT:MEMFF
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
"DESDIR:H:/fpga_test/cmos_fifo_usb/smartgen\soft_fifo1280x8"
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS2X2M1
SMARTGEN_PACKAGE:vq100
WWIDTH:8
WDEPTH:1280
RWIDTH:16
RDEPTH:640
CLKS:2
WCLOCK_PN:WCLOCK
RCLOCK_PN:RCLOCK
WCLK_EDGE:RISE
RCLK_EDGE:RISE
ACLR_PN:RESET
RESET_POLARITY:0
INIT_RAM:F
WE_POLARITY:0
RE_POLARITY:0
FF_PN:FULL
AF_PN:AFULL
WACK_PN:WACK
OVRFLOW_PN:OVERFLOW
WRCNT_PN:WRCNT
WE_PN:WE
EF_PN:EMPTY
AE_PN:AEMPTY
DVLD_PN:DVLD
UDRFLOW_PN:UNDERFLOW
RDCNT_PN:RDCNT
RE_PN:RE
CONTROLLERONLY:F
FSTOP:YES
ESTOP:YES
WRITEACK:NO
OVERFLOW:NO
WRCOUNT:NO
DATAVALID:NO
UNDERFLOW:NO
RDCOUNT:NO
AF_PORT_PN:AFVAL
AE_PORT_PN:AEVAL
AFFLAG:NONE
AEFLAG:NONE
DATA_IN_PN:DATA
DATA_OUT_PN:Q