2410init.s

三星ARM2410的WDT看门狗程序实验

		;// Set GPF4=0 GPF5=1 GPF6=1 GPF7=1
		LDR	R0, =GPFDAT
		LDR	R1, =0xE0
		STR	R1, [R0]
	]
	
	;// Check weather the boot is caused by the wake-up from POWER_OFF mode
	LDR	R1, =GSTATUS2
	LDR	R0, [R1]
	TST	R0, #0x2
    
    ;// In case of the wake-up from POWER_OFF mode, go to POWER_OFF_WAKEUP handler.
	BNE	WAKEUP_POWER_OFF
	
StartPointAfterPowerOffWakeUp
	
	;// Setup memory control registers
	LDR	R0, =SMRDATA
	LDR	R1, =BWSCON				;// BWSCON Address
	ADD	R2, R0, #52				;// End address of SMRDATA
	
Ram_Init
	LDR	R3, [R0], #4
	STR	R3, [R1], #4
	CMP	R2, R0
	BNE	Ram_Init
	
	[ NAND_FLASH_BOOT
		
		;// We boot from NAND Flash
		LDR	R0,	=_RAMBASE		;// Destination
		LDR	R1,	=0x0			;// Start position in NAND Flash
		LDR	R2,	=|Image$$RW$$Limit|
		LDR	R3,	=|Image$$RW$$Base|
		SUB	R2,	R2,	R3
		LDR	R3,	=|Image$$RO$$Limit|
		ADD	R2,	R2,	R3
		LDR	R3,	=|Image$$RO$$Base|
		SUB	R2,	R2,	R3
		BL	nand_copy			;// Copy to RAM
	|
		;// We boot from NOR Flash
		LDR	R0,	=|Image$$RO$$Base|
		LDR	R1,	=|Image$$RO$$Limit|
		LDR	R2,	=_RAMBASE
		
		;// Copy RO area to RAM
Copy_RO_Area
		CMP		R0,	R1
		LDRLS	R3,	[R0],	#4
		STRLS	R3,	[R2],	#4
		BLS		Copy_RO_Area
	]
	
	;// "Reboot" without init from RAM
	LDR		PC,	=_RAMBASE

StartfromRam
	
	;// Initialize stacks
	BL	InitStacks
	
	;// Setup IRQ handler
	LDR	R0, =HandleIRQ
	LDR	R1, =IsrIRQ
	STR	R1, [R0]
	
	;// Copy RW area and clear ZI
	
StartcopyRW
	LDR	R0, =|Image$$RO$$Limit|		;// Get pointer to RW data area ( RW source base )
	LDR	R1, =|Image$$RW$$Base|		;// RW destination base
	LDR	R2, =|Image$$ZI$$Base|		;// Zero base
	LDR	R3, =|Image$$ZI$$Limit|		;// Limit of zero init segment
	
	[ NAND_FLASH_BOOT
		;// We've copy RO to ram. So RO now is RO + _RAMBASE
		LDR	R4,	=_RAMBASE
		ADD	R0,	R0,	R4
	]
	
	;// Skip copy RW?
	CMP	R0,	R1
	BEQ	Init_Zero_Start
	
	;// Copy RW area
Copy_RW_Area
	CMP		R1,	R2
	LDRLS	R4,	[R0],	#4
	STRLS	R4,	[R1],	#4
	BLS		Copy_RW_Area
	
Init_Zero_Start
	LDR		R4,	=0x00
	
Init_Zero
	;// Zero area initialize
	CMP		R2, R3
	STRLS	R4, [R2],	#4
	BLS		Init_Zero
	
Startmain
	[ {CONFIG} = 16
		;// Change mode to Thumb
		ORR	LR, PC, #1
		BX	LR
		THUMB
		B	main
		ARM
	|
		[ DEBUGLEDS_TYPE = 1
			;// Set GPG8=1 GPG9=1
			LDR	R0, =GPGDAT
			LDR	R1, =0x0000
			STR	R1, [R0]
		]
		[ DEBUGLEDS_TYPE = 2
			;// Set GPF4=0 GPF5=0 GPF6=0 GPF7=0
			LDR	R0, =GPFDAT
			LDR	R1, =0x0000
			STR	R1, [R0]
		]
		B	main
	]
	
;//---------------------------------------------------------------------------
;// Function: Initializing stacks
;//---------------------------------------------------------------------------
InitStacks
	
	MRS	R0, CPSR
	BIC	R0, R0, #MODEMASK
	
	;// Undef Mode stacks
	ORR	R1, R0, #UNDEFMODE|NOINT
	MSR	cpsr_cxsf, R1
	LDR	SP, =UndefStack
	
	;// Abort Mode stack
	ORR	R1, R0, #ABORTMODE|NOINT
	MSR	cpsr_cxsf, R1
	LDR	SP, =AbortStack
	
	;// IRQ Mode stack
	ORR	R1, R0, #IRQMODE|NOINT
	MSR	cpsr_cxsf, R1
	LDR	SP, =IRQStack
	
	;// FIQ Mode stack
	ORR	R1, R0, #FIQMODE|NOINT
	MSR	cpsr_cxsf, R1
	LDR	SP, =FIQStack
	
	;// Service Mode stack
	BIC	R0,	R0,	#MODEMASK|NOINT
	ORR	R1 ,R0, #SVCMODE
	MSR	cpsr_cxsf, R1
	LDR	SP, =SVCStack
	
	;// User mode has not be initialized.
	
	;// The LR register won't be valid if the current mode is not Service mode.
	MOV	PC, LR
	
	LTORG
	
;//---------------------------------------------------------------------------
;// Function: Wakeup from POWER_OFF Mode
;//---------------------------------------------------------------------------
WAKEUP_POWER_OFF
	
	;// Release SCLKn after wake-up from the POWER_OFF mode
	LDR	R1, =MISCCR
	LDR	R0, [R1]
	BIC	R0, R0, #( 7 << 17 )	;// SCLK0:0->SCLK SCLK1:0->SCLK SCKE:L->H
	STR	R0, [R1]
	
	;// Set memory control registers
	LDR	R0, =SMRDATA
	LDR	R1, =BWSCON				;// BWSCON Address
	ADD	R2, R0, #52				;// End address of SMRDATA
	
Wakeup_Ram_Init
	LDR	R3, [R0], #4
	STR	R3, [R1], #4
	CMP	R2, R0
	BNE	Wakeup_Ram_Init
	
	;// Wait for 256 until the SelfRefresh is released
	MOV	R1, #256
Wakeup_Wait
	SUBS	R1, R1, #1
	BNE	Wakeup_Wait
	
	;// Restore PC
	LDR	R1, =GSTATUS3			;// GSTATUS3 has the start address just after POWER_OFF wake-up
	LDR	R0, [R1]
	MOV	PC, R0
	
	LTORG

;//============================================================================
;// SDRAM control register value table
;//============================================================================
SMRDATA
	
	;// Notice:
	;// 1. If you are bootting from NAND Flash. THE FOLLOWING DATA MUST BE IN THE 4K RANGE.
	;// 2. If you want to change memory config parameters, see memconfig.inc
	;// 3. Memory configuration should be optimized for best performance
	;//    The following parameter is not optimized
	;// 4. Memory access cycle parameter strategy:
	;//    The memory settings is safe parameters even at HCLK = 75Mhz
	;//    SDRAM refresh period is for HCLK = 75Mhz	
	
	DCD	(0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))	;//BWSCON
	
	DCD	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))	;// BANKCON0
	DCD	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))	;// BANKCON1
	DCD	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))	;// BANKCON2
	DCD	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))	;// BANKCON3
	DCD	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))	;// BANKCON4
	DCD	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))	;// BANKCON5
	DCD	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))														;// BANKCON6
	DCD	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))														;// BANKCON7
	
	DCD	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)							;// REFRESH
	DCD	((BURST_EN<<7)+(SCKE_EN<<5)+(SCLK_EN<<4)+BK76MAP)											;// BANKSIZE
	DCD	((B6_WBL<<9)+(B6_TM<<7)+(B6_CL<<4)+(B6_BT<<3)+B6_BL)										;// MRSRB6
	DCD	((B7_WBL<<9)+(B7_TM<<7)+(B7_CL<<4)+(B7_BT<<3)+B7_BL)										;// MRSRB7
	
	ALIGN
	
;//============================================================================
;// Interrupt Handlers table in RAM ( Use for C/C++ to set interrupt function )
;//============================================================================
	AREA RamData, DATA, READWRITE
	
	;// Notice:
	;// 1. The following data is in the RW part.
	;// 2. The following data is used for C/C++ to set interrupt handler function address.
	;// 3. The following data WON'T BE USED DIRECTLY, but call by a light weight interrupt handler
	;//    which is used jump to the handler function.
	^	_ISR_STARTADDRESS
	;// Internal interrupts
HandleReset		#	4
HandleUndef		#	4
HandleSWI		#	4
HandlePabort	#	4
HandleDabort	#	4
HandleReserved	#	4
HandleIRQ		#	4
HandleFIQ		#	4
	;// External interrupts
HandleEINT0		#	4
HandleEINT1		#	4
HandleEINT2		#	4
HandleEINT3		#	4
HandleEINT4_7	#	4
HandleEINT8_23	#	4
HandleRSV6		#	4
HandleBATFLT	#	4
HandleTICK		#	4
HandleWDT		#	4
HandleTIMER0	#	4
HandleTIMER1	#	4
HandleTIMER2	#	4
HandleTIMER3	#	4
HandleTIMER4	#	4
HandleUART2		#	4
HandleLCD		#	4
HandleDMA0		#	4
HandleDMA1		#	4
HandleDMA2		#	4
HandleDMA3		#	4
HandleMMC		#	4
HandleSPI0		#	4
HandleUART1		#	4
HandleRSV24		#	4
HandleUSBD		#	4
HandleUSBH		#	4
HandleIIC		#	4
HandleUART0		#	4
HandleSPI1		#	4
HandleRTC		#	4
HandleADC		#	4

	END