2410init.s

三星 ARM2410UART的通信实验程序

;===============================================================================
;--------------------------------- Copy Left -----------------------------------
;						Illidan Fly's Project
;						Power by BigFly Network
;						http://bigfly.happybobby.com
;						
;						Released under GPL2 License
;
;----------------------------- File Description --------------------------------
; Filename:	2410init.s
; Date:		2007.01.13
; Version:	0.0.10
; Description:
;			Startup code for s3c2410.
;			1. Initialize hardware ( PLL / Debug LEDs / NAND Flash / SDRAM )
;			2. Initialize stacks for C/C++ program
;			3. Provide rewritable interrupt entry function table
;			4. Support boot code from NAND / NOR Flash
;			5. Support ARM/THUMB code mode
;			6. Support Big-endian / Little-endian mode
;			7. Support wakeup from PowerDown mode
;
;----------------------------- Version History ---------------------------------
; 0.0.10: Fix interrupt and monitor compatible issues
; 0.0.9: Rewrite code for RVDS
; 0.0.8: Several issue fix
; 0.0.7: Fix interrupts' return address
; 0.0.6: Add NAND Flash boot code
; 0.0.5: Fix some bugs and add PLL initialization
; 0.0.4: Add target board leds flash
; 
; ** Maintenance started from BigFly Network **
; 
; 0.0.3: Sub interrupt disable 0x3ff -> 0x7ff ( By SJS )
; 0.0.2: Add some functions for testing STOP,POWER_OFF mode ( By purnnamu )
; 0.0.1: First release ( By kwtark )
;
;===============================================================================

;//============================================================================
;// Include part
;//============================================================================

;// !! WARNING: DO NOT TRIM THE SPACE OF THE FOLLOWING INC, OR YOU WILL GET A ERROR !!

	GET option.inc		;// Options ( Stack, RAM Base, etc... )
	GET memconfig.inc	;// Memory config
	GET 2410addr.inc	;// 2410 address table

;//============================================================================
;// Configuration part
;//============================================================================

	GBLL 	PLL_ON_START
	GBLA	DEBUGLEDS_TYPE
	GBLA	ENTRY_BUS_WIDTH
	GBLL	NAND_FLASH_BOOT
	
PLL_ON_START	SETL	{TRUE}		;// Set PLL register on boot?
DEBUGLEDS_TYPE	SETA	2			;// Debug LEDs type
ENTRY_BUS_WIDTH	SETA	16			;// Entry bus width
NAND_FLASH_BOOT	SETL	{FALSE}		;// Nand Flash boot?

;// The base of stacks for every mode
UserStack	EQU		( _STACK_BASEADDRESS - 0x3800 )	;// 0x33ff4800 ~
SVCStack	EQU		( _STACK_BASEADDRESS - 0x2800 )	;// 0x33ff5800 ~
UndefStack	EQU		( _STACK_BASEADDRESS - 0x2400 )	;// 0x33ff5c00 ~
AbortStack	EQU		( _STACK_BASEADDRESS - 0x2000 )	;// 0x33ff6000 ~
IRQStack	EQU		( _STACK_BASEADDRESS - 0x1000 )	;// 0x33ff7000 ~
FIQStack	EQU		( _STACK_BASEADDRESS - 0x0000 )	;// 0x33ff8000 ~

;//============================================================================
;// Constants part
;//============================================================================

;// Pre-defined constants
USERMODE	EQU		0x10
FIQMODE		EQU		0x11
IRQMODE		EQU		0x12
SVCMODE		EQU		0x13
ABORTMODE	EQU		0x17
UNDEFMODE	EQU		0x1b
MODEMASK	EQU		0x1f
NOINT		EQU		0xc0

;//============================================================================
;// Macros part
;//============================================================================
	
;// Marco for LR return in different mode
	MACRO
	MOV_PC_LR
		[ {CONFIG} = 16
			BX	LR
		|
			MOV	PC,LR
		]
	MEND
	
;// Marco for handler of interrupts ( except Reset interrupt )
	MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
	PUSH	{R0, R1}			;// PUSH the work register to stack & one reserved for PC
	LDR		R0, =$HandleLabel	;// Load the address of Handle
	LDR		R0, [R0]
	STR		R0, [SP, #4]		;// Store the ISR entry to stack
	POP		{R0, PC}			;// POP the work register and PC ( jump to ISR )
	MEND

;//============================================================================
;// Import/Export part
;//============================================================================
	
	;// In this part, the ARM Linker will import/export the address of the
	;// following entry. It's very useful to link with C/C++ function
	
	IMPORT	|Image$$RO$$Base|	;// Base of ROM code
	IMPORT	|Image$$RO$$Limit|	;// End of ROM code ( = Start of ROM data )
	IMPORT	|Image$$RW$$Base|	;// Base of RAM to initialise
	IMPORT	|Image$$RW$$Limit|	;// Limit of RAM to initialise
	IMPORT	|Image$$ZI$$Base|	;// Base of zero area (BSS)
	IMPORT	|Image$$ZI$$Limit|	;// Limit of zero area (BSS)
	
	IMPORT	nand_copy			;// NAND Flash copy function
	IMPORT	main				;// The main entry of the C/C++ program
	
	EXPORT	StartPointAfterPowerOffWakeUp	;// PowerOff wakeup
	
;//============================================================================
;// Program part
;//============================================================================

	PRESERVE8
	AREA	Init,CODE,READONLY
	
	;// Tell ARM Linker this is the image entry
	ENTRY
	
	[ {CONFIG} = 16
		ARM
	]
	
	[ BIGENDIAN_MODE
		
		;// Notice:
		;// 1. The code, which converts cpu to Big-endian mode, should be a Little-endian code.
		;// 2. The following Little-endian code will be compiled in Big-Endian mode.
		;//    The code byte order should be changed as the memory bus width.
		
		[ ENTRY_BUS_WIDTH = 32
			B	ChangeBigEndian			;// DCD 0xea000007
		]
		
		[ ENTRY_BUS_WIDTH = 16
			ANDEQ	R14,R7,R0,LSL #20	;// DCD 0x0007ea00
		]
		
		[ ENTRY_BUS_WIDTH = 8
			STREQ	R0,[R0,-R10,ROR #1]	;// DCD 0x070000ea
		]
	|
		B	ResetHandler	;// Handler for Reset
	]
	
	B	HandlerUndef	;// Handler for Undefined mode
	B	HandlerSWI		;// Handler for SWI interrupt
	B	HandlerPabort	;// Handler for Prefetch abort
	B	HandlerDabort	;// Handler for Data abort
	B	.				;// Reserved
	B	HandlerIRQ		;// Handler for IRQ interrupt
	B	HandlerFIQ		;// Handler for FIQ interrupt
	
	[ BIGENDIAN_MODE
		
ChangeBigEndian
		
		[ ENTRY_BUS_WIDTH = 32
			DCD	0xee110f10	;// 0xee110f10 => MRC P15,0,R0,C1,C0,0
			DCD	0xe3800080	;// 0xe3800080 => ORR R0,R0,#0x80		;//Big-endian
			DCD	0xee010f10	;// 0xee010f10 => MRC P15,0,R0,C1,C0,0
		]
		[ ENTRY_BUS_WIDTH = 16
			DCD 0x0f10ee11
			DCD 0x0080e380
			DCD 0x0f10ee01
		]
		[ ENTRY_BUS_WIDTH = 8
			DCD 0x100f11ee
			DCD 0x800080e3
			DCD 0x100f01ee
		]
		
		DCD 0xffffffff	;// Swinv 0xffffff is similar with NOP and run well in both endian mode.
		DCD 0xffffffff
		DCD 0xffffffff
		DCD 0xffffffff
		DCD 0xffffffff
	
		B	ResetHandler
	]

;//---------------------------------------------------------------------------
;// Interrupt Handlers
;//---------------------------------------------------------------------------
	;// Notice:
	;// 1. The following interrupts are sort by priority but the order isn't important for programming.

HandlerDabort	HANDLER HandleDabort
HandlerFIQ		HANDLER HandleFIQ
HandlerIRQ		HANDLER HandleIRQ
HandlerPabort	HANDLER HandlePabort

HandlerUndef	HANDLER HandleUndef
HandlerSWI		HANDLER HandleSWI

IsrIRQ
	PUSH	{R0, R1}		;// Reserved for PC
	PUSH	{R8, R9}
	LDR		R9, =INTOFFSET
	LDR		R9, [R9]
	LDR		R8, =HandleEINT0
	ADD		R8, R8, R9, LSL #2
	LDR		R8, [R8]
	STR		R8, [SP, #12]
	POP		{R8, R9}
	POP		{R0, PC}
	
;//---------------------------------------------------------------------------
;// Reset Handler
;//---------------------------------------------------------------------------
ResetHandler
	
	;// If we start from ram, jump to copy rw
	MOV	R0,	PC
	LDR	R1,	=_RAMBASE
	CMP	R0,	R1
	BHS	StartfromRam
	
	;// Disable watch dog
	LDR	R0, =WTCON
	LDR	R1, =0x0000
	STR	R1, [R0]
	
	;// Mask all interrupt
	LDR	R0, =INTMSK
	LDR	R1, =0xFFFFFFFF
	STR	R1, [R0]
	
	;// Mask all sub interrupt
	LDR	R0, =INTSUBMSK
	LDR	R1, =0x000007FF
	STR	R1, [R0]
	
	;// Adjust PLL lock time count register
	LDR	R0, =LOCKTIME
	LDR	R1, =0x00FFFFFF
	STR	R1, [R0]
	
	[ PLL_ON_START
		;// Configure MPLL according PLL options
		LDR	R0, =MPLLCON
		LDR	R1, =( ( M_MDIV << 12 ) + ( M_PDIV << 4 ) + M_SDIV )
		STR	R1, [R0]
		
		;// Configure CLK Divider register
		;// FCLK:HCLK:PCLK = 1:2:4
		LDR	R0, =CLKDIVN
		LDR	R1, =( ( 0 << 2 ) + ( 1 << 1 ) + 1 )
		STR	R1, [R0]
	]
	
	;// Turn on the debug LEDs on the board
	[ DEBUGLEDS_TYPE = 1
		;// Set GPG8 GPG9 to output
		LDR	R0, =GPGCON
		LDR	R1, =0x00050000
		STR	R1, [R0]
		;// Set GPG8=0 GPG9=1
		LDR	R0, =GPGDAT
		LDR	R1, =0x0200
		STR	R1, [R0]
	]
	[ DEBUGLEDS_TYPE = 2
		;// Set GPF4 GPF5 GPF6 GPF7 to output
		LDR	R0, =GPFCON
		LDR	R1, =0x5500
		STR	R1, [R0]