nandboot.c

三星 ARM2410UART的通信实验程序

/*=============================================================================
--------------------------------- Copy Left -----------------------------------
						Illidan Fly's Project
						Power by BigFly Network
						http://bigfly.happybobby.com
						
						Released under GPL2 License

----------------------------- File Description --------------------------------
 Filename:	nandboot.c
 Date:		2006.11.27
 Version:	0.0.1
 Description:
			NAND Flash boot support for s3c2410.
----------------------------- Version History ---------------------------------
 0.0.1: First release

=============================================================================*/

// NAND Flash controller registers' addresses
#define rNFCONF		(*(volatile unsigned int  *)0x4e000000)
#define rNFCMD		(*(volatile unsigned char *)0x4e000004)
#define rNFADDR		(*(volatile unsigned char *)0x4e000008)
#define rNFDATA		(*(volatile unsigned char *)0x4e00000c)
#define rNFSTAT		(*(volatile unsigned int  *)0x4e000010)
#define rNFECC		(*(volatile unsigned int  *)0x4e000014)
#define rNFECC0		(*(volatile unsigned char *)0x4e000014)
#define rNFECC1		(*(volatile unsigned char *)0x4e000015)
#define rNFECC2		(*(volatile unsigned char *)0x4e000016)

// Marco for NAND Flash operation
#define WRITE_NAND_COMMAND(d) 	do{rNFCMD = d;}while(0)
#define WRITE_NAND_ADDRESS(d)	do{rNFADDR = d;}while(0)
#define WRITE_NAND(d)			do{rNFDATA = d;}while(0)
#define READ_NAND()				(rNFDATA)
#define NAND_WAIT_READY()		{while(!(rNFSTAT&(1<<0)));}
#define NAND_DISABLE_CE()		{rNFCONF |= (1<<11);}
#define NAND_ENABLE_CE()		{rNFCONF &= ~(1<<11);}

// NAND Flash configuration
#define SECTORSIZE				512				// Size of one page (in byte)
#define NAND_SECTOR_SIZE		SECTORSIZE
#define NAND_TWRPH0				4
#define NAND_TWRPH1				4
#define NAND_TACLS				4
#define NAND_INITECC			1
#define NAND_CONTROLLER_ENABLE	1

// NAND Flash command
#define NAND_CMD_RESET		0xFF
#define NAND_CMD_READ		0x00

void nand_reset(void)
{
	int i;
	
	// Init flash controller and chip
	rNFCONF=((NAND_CONTROLLER_ENABLE<<15)|(NAND_INITECC<<12)|(1<<11)|(NAND_TACLS<<8)|(NAND_TWRPH0<<4)|(NAND_TWRPH1<<0));
	
	NAND_ENABLE_CE();					// Chip enabled
	WRITE_NAND_COMMAND(NAND_CMD_RESET);	// Send reset command
	for(i=0;i<10;i++){;}				// Wait 100ns
	NAND_WAIT_READY();					// Wait 200~500us
	NAND_DISABLE_CE();					// Chip disabled
}

int nand_copy(unsigned char *buf, unsigned long start_addr, int size)
{	
	int i,j;
	
	nand_reset();
	
	NAND_ENABLE_CE();
	
	// Wait 100ns
	for(i=0;i<10;i++){;}
	
	i = start_addr;
	
	while(i < start_addr + size)
	{
		// Send read command
		rNFCMD = NAND_CMD_READ;
		
		// Send address
		rNFADDR = i & 0xff;
		rNFADDR = (i >> 9) & 0xff;
		rNFADDR = (i >> 17) & 0xff;
		rNFADDR = (i >> 25) & 0xff;
		NAND_WAIT_READY();
		
		// Read a page to buf
		for(j=0;j < NAND_SECTOR_SIZE;j++,i++)
		{
			*buf = (rNFDATA & 0xff);
			buf++;
		}
	}
	NAND_DISABLE_CE();
	
	return 0;
}