ex8_8.mdl

线性调频信号通过匹配滤波器的程序 还有一些simulink仿真模型

Model {
  Name			  "ex7_9"
  Version		  2.09
  SimParamPage		  Solver
  SampleTimeColors	  off
  InvariantConstants	  off
  WideVectorLines	  off
  ShowLineWidths	  off
  PaperOrientation	  landscape
  PaperType		  usletter
  PaperUnits		  inches
  StartTime		  "0.0"
  StopTime		  "10.0"
  Solver		  ode45
  RelTol		  "1e-3"
  AbsTol		  "1e-6"
  Refine		  "1"
  MaxStep		  "auto"
  InitialStep		  "auto"
  FixedStep		  "auto"
  MaxOrder		  5
  OutputOption		  RefineOutputTimes
  OutputTimes		  "[]"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  LimitMaxRows		  off
  MaxRows		  "1000"
  Decimation		  "1"
  AlgebraicLoopMsg	  warning
  MinStepSizeMsg	  warning
  UnconnectedInputMsg	  warning
  UnconnectedOutputMsg	  warning
  UnconnectedLineMsg	  warning
  ConsistencyChecking	  off
  ZeroCross		  on
  SimulationMode	  normal
  RTWSystemTargetFile	  "grt.tlc"
  RTWInlineParameters	  off
  RTWRetainRTWFile	  off
  RTWTemplateMakefile	  "grt_vc.tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  BlockDefaults {
    Orientation		    right
    ForegroundColor	    black
    BackgroundColor	    white
    DropShadow		    off
    NamePlacement	    normal
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    normal
    FontAngle		    normal
    ShowName		    on
  }
  AnnotationDefaults {
    HorizontalAlignment	    center
    VerticalAlignment	    middle
    ForegroundColor	    black
    BackgroundColor	    white
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    normal
    FontAngle		    normal
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    normal
    FontAngle		    normal
  }
  System {
    Name		    "ex7_9"
    Location		    [187, 245, 426, 374]
    Open		    on
    ScreenColor		    white
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem2"
      Ports		      [2, 1, 0, 0, 0]
      Position		      [30, 29, 90, 76]
      ShowName		      off
      ShowPortLabels	      on
      MaskType		      "AND Gate"
      MaskDescription	      "This is a masked block that implements a "
			      "2 input AND gate."
      MaskHelp		      "The AND block contains a logic block configured "
			      "as a 2 input AND gate. There are no configuratio"
			      "n parameters."
      MaskInitialization      "t=-pi/2:0.1:pi/2 ;"
      MaskDisplay	      "plot([0.5,0,0,0.5],[0,0,1,1],0.5+0.5*cos(t),0.5+"
			      "0.5*sin(t)) \n\ntext(0.05,0.65,'a');            "
			      "                                                "
			      "                       \ntext(0.05,0.2,'b');    "
			      "                                                "
			      "                                \ntext(0.75,0.45"
			      ",'ab');   "
      MaskIconFrame	      off
      MaskIconOpaque	      on
      MaskIconRotate	      port
      MaskIconUnits	      normalized
      System {
	Name			"Subsystem2"
	Location		[496, 199, 666, 283]
	Open			off
	ScreenColor		white
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 28, 55, 42]
	  Port			  "1"
	  PortWidth		  "-1"
	  SampleTime		  "-1"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 43, 55, 57]
	  Port			  "2"
	  PortWidth		  "-1"
	  SampleTime		  "-1"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Gate1"
	  Ports			  [2, 1, 0, 0, 0]
	  Position		  [60, 27, 90, 58]
	  Operator		  AND
	  Inputs		  "2"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [115, 38, 145, 52]
	  Port			  "1"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Gate1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Gate1"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Gate1"
	  DstPort		  2
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem3"
      Ports		      [2, 1, 0, 0, 0]
      Position		      [140, 29, 195, 71]
      ShowName		      off
      ShowPortLabels	      on
      MaskType		      "OR Gate"
      MaskDescription	      "This block implements an OR gate"
      MaskInitialization      "t=0:0.1:1;"
      MaskDisplay	      "plot([0,0],[0,1],t,0.5*t.^2,t,1-0.5*t.^2);      "
			      "                                                "
			      "       \ntext(0.05,0.65,'a');                   "
			      "                                                "
			      "                \ntext(0.05,0.2,'b');           "
			      "                                                "
			      "                         \ntext(0.6,0.45,'a+b');"
			      "      "
      MaskIconFrame	      off
      MaskIconOpaque	      on
      MaskIconRotate	      port
      MaskIconUnits	      normalized
      System {
	Name			"Subsystem3"
	Location		[571, 164, 761, 248]
	Open			off
	ScreenColor		white
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 28, 55, 42]
	  Port			  "1"
	  PortWidth		  "-1"
	  SampleTime		  "-1"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 43, 55, 57]
	  Port			  "2"
	  PortWidth		  "-1"
	  SampleTime		  "-1"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Gate1"
	  Ports			  [2, 1, 0, 0, 0]
	  Position		  [80, 27, 110, 58]
	  Operator		  OR
	  Inputs		  "2"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [135, 38, 165, 52]
	  Port			  "1"
	  OutputWhenDisabled	  held
	  InitialOutput		  "0"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Gate1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Gate1"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Gate1"
	  DstPort		  2
	}
      }
    }
  }
}