prev_cmp_sdh_top.map.qmsg

该程序是同步帧检测

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 22 02:32:41 2008 " "Info: Processing started: Thu May 22 02:32:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sdh_top -c sdh_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sdh_top -c sdh_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdh_clk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sdh_clk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdh_clk-clk_proc " "Info: Found design unit 1: sdh_clk-clk_proc" {  } { { "sdh_clk.vhd" "" { Text "E:/fram/sdh_clk.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sdh_clk " "Info: Found entity 1: sdh_clk" {  } { { "sdh_clk.vhd" "" { Text "E:/fram/sdh_clk.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdh_fifo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sdh_fifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdh_fifo-arch_blockdram " "Info: Found design unit 1: sdh_fifo-arch_blockdram" {  } { { "sdh_fifo.vhd" "" { Text "E:/fram/sdh_fifo.vhd" 36 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sdh_fifo " "Info: Found entity 1: sdh_fifo" {  } { { "sdh_fifo.vhd" "" { Text "E:/fram/sdh_fifo.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdh_frame_synchro.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sdh_frame_synchro.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdh_frame_synchro_capture-sdh_frame_synchro_capture " "Info: Found design unit 1: sdh_frame_synchro_capture-sdh_frame_synchro_capture" {  } { { "sdh_frame_synchro.vhd" "" { Text "E:/fram/sdh_frame_synchro.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sdh_frame_synchro_capture " "Info: Found entity 1: sdh_frame_synchro_capture" {  } { { "sdh_frame_synchro.vhd" "" { Text "E:/fram/sdh_frame_synchro.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdh_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sdh_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdh_transact_top-sdh_transact_top " "Info: Found design unit 1: sdh_transact_top-sdh_transact_top" {  } { { "sdh_top.vhd" "" { Text "E:/fram/sdh_top.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sdh_transact_top " "Info: Found entity 1: sdh_transact_top" {  } { { "sdh_top.vhd" "" { Text "E:/fram/sdh_top.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "syn_ramstyle sdh_fifo.vhd(41) " "Error (10482): VHDL error at sdh_fifo.vhd(41): object \"syn_ramstyle\" is used but not declared" {  } { { "sdh_fifo.vhd" "" { Text "E:/fram/sdh_fifo.vhd" 41 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu May 22 02:32:42 2008 " "Error: Processing ended: Thu May 22 02:32:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}