acacia.h

IDT RC32438 on-chip ethernet controller

/*
 *
 * BRIEF MODULE DESCRIPTION
 *      Helpfile for acacia.c
 *
 * Author: MontaVista Software, Inc.
 *         	[e-mail] or [e-mail]
 *
 * Heavily modified from original version by:
 *	Author: Integrated Device Technology, Inc.
 *	Haofeng Kou:		Design and modify the code. 
 *
 * ########################################################################
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * ########################################################################
 */

#ifndef ACACIA_H
#define ACACIA_H

#include <linux/config.h>
#include  <asm/rc32438/types.h> 
#include  <asm/rc32438/dma_v.h>
#include  <asm/rc32438/eth_v.h>


/* This is for ZA/ZC part debug */
#define	RC32438_REVISION_ZA	

#define 	ACACIA_DEBUG	2
#define 	ACACIA_PROC_DEBUG
#undef	ACACIA_DEBUG
#undef	ACACIA_PROC_DEBUG

#ifdef ACACIA_DEBUG

/* use 0 for production, 1 for verification, >2 for debug */
static int acacia_debug = ACACIA_DEBUG;
/*ASSERT*/
#define ASSERT(expr) \
	if(!(expr)) {	\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
		#expr,__FILE__,__FUNCTION__,__LINE__);		}
/*DBG*/
#define DBG(lvl, format, arg...) if (acacia_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
/*ERR WARN*/
#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)		
				    
#else

#define ASSERT(expr) do {} while (0)
#define DBG(lvl, format, arg...) do {} while (0)
#define ERR(format, arg...) do {} while (0)
#define WARN(format, arg...) do {} while (0)

#endif

#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)


#define ETH0_DMA_RX_IRQ   GROUP1_IRQ_BASE + 2
#define ETH0_DMA_TX_IRQ   GROUP1_IRQ_BASE + 3
#define ETH0_RX_OVR_IRQ   GROUP3_IRQ_BASE + 12
#define ETH0_TX_UND_IRQ   GROUP3_IRQ_BASE + 13
#define ETH1_DMA_RX_IRQ   GROUP1_IRQ_BASE + 4
#define ETH1_DMA_TX_IRQ   GROUP1_IRQ_BASE + 5
#define ETH1_RX_OVR_IRQ   GROUP3_IRQ_BASE + 15
#define ETH1_TX_UND_IRQ   GROUP3_IRQ_BASE + 16

extern unsigned int idt_cpu_freq;

/* Index to functions, as function prototypes. */
#ifdef	RC32438_REVISION_ZA	
static void acacia_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
#endif
static int acacia_open(struct net_device *dev);
static int acacia_send_packet(struct sk_buff *skb, struct net_device *dev);
//static void acacia_mii_handler(unsigned long data);
static void acacia_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
static void acacia_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
static void acacia_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
static int  acacia_close(struct net_device *dev);
static struct net_device_stats *acacia_get_stats(struct net_device *dev);
static void acacia_multicast_list(struct net_device *dev);
static int  acacia_init(struct net_device *dev);
static void acacia_tx_timeout(struct net_device *dev);
static void acacia_tx_tasklet(unsigned long tx_data_dev);
static void acacia_rx_tasklet(unsigned long rx_data_dev);
static void acacia_cleanup_module(void);
static int acacia_probe(int port_num);
int acacia_init_module(void);


/* the following must be powers of two */
#if CONFIG_NET_FASTROUTE
#define ACACIA_NUM_RDS    512    		/* number of receive descriptors */
#define ACACIA_NUM_TDS    512    		/* number of transmit descriptors */
#else
#define ACACIA_NUM_RDS    128    		/* number of receive descriptors */
#define ACACIA_NUM_TDS    128    		/* number of transmit descriptors */
#endif


#define ACACIA_RBSIZE     1536  		/* size of one resource buffer = Ether MTU */
#define ACACIA_RDS_MASK   (ACACIA_NUM_RDS-1)
#define ACACIA_TDS_MASK   (ACACIA_NUM_TDS-1)
#define RD_RING_SIZE (ACACIA_NUM_RDS * sizeof(struct DMAD_s))
#define TD_RING_SIZE (ACACIA_NUM_TDS * sizeof(struct DMAD_s))

#define ACACIA_TX_TIMEOUT HZ * 100

#define rc32438_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
#define rc32438_eth1_regs ((ETH_t)(ETH1_VirtualAddress))

enum status	{ filled,	empty};
#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)


/*
 * This is board-specific data that is stored in a "fixed" location in flash.
 * It is shared across operating systems, so it should not be changed lightly.
 * The main reason we need it is in order to extract the ethernet MAC
 * address(es).
 */
struct idt32438_boarddata {
    u32 magic;                       /* board data is valid */
#define IDT32438_BD_MAGIC 0x50423332   /* "PB32" */
    u16 cksum;                       /* checksum (starting with BD_REV 2) */
    u16 rev;                         /* revision of this struct */
#define BD_REV  4
    char   boardName[64];            /* Name of board */
    u16 major;                       /* Board major number */
    u16 minor;                       /* Board minor number */
    u32 config;                      /* Board configuration */
#define BD_ENET0        0x00000001   /* ENET0 is stuffed */
#define BD_ENET1        0x00000002   /* ENET1 is stuffed */
#define BD_UART1        0x00000004   /* UART1 is stuffed */
#define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
#define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
#define BD_SYSLED       0x00000020   /* System LED stuffed */
#define BD_EXTUARTCLK   0x00000040   /* External UART clock */
#define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
#define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
#define BD_WLAN0        0x00000200   /* use WLAN0 */
#define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
#define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
#define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
#define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
#define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
#define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
#define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
#define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
    u16 resetConfigGpio;             /* Reset factory GPIO pin */
    u16 sysLedGpio;                  /* System LED GPIO pin */

    u32 cpuFreq;                     /* CPU core frequency in Hz */
    u32 sysFreq;                     /* System frequency in Hz */
    u32 cntFreq;                     /* Calculated C0_COUNT frequency */

    u8  wlan0Mac[6];
    u8  enet0Mac[6];
    u8  enet1Mac[6];

    u16 pciId;                       /* Pseudo PCIID for common code */
    u16 memCap;                      /* cap bank1 in MB */

    /* version 3 */
    u8  wlan1Mac[6];                 /* (ar5212) */
};


/* Information that need to be kept for each board. */
struct acacia_local {
	ETH_t  eth_regs;
	DMA_Chan_t  rx_dma_regs;
	DMA_Chan_t  tx_dma_regs;
 	volatile DMAD_t   td_ring;  					/* transmit descriptor ring */ 
	volatile DMAD_t   rd_ring;  					/* receive descriptor ring  */

	struct sk_buff* tx_skb[ACACIA_NUM_TDS]; 	/* skbuffs for pkt to trans */
	struct sk_buff* rx_skb[ACACIA_NUM_RDS]; 	/* skbuffs for pkt to trans */

	struct tasklet_struct * rx_tasklet;
	struct tasklet_struct * tx_tasklet;

	int	rx_next_done;
	int	rx_chain_head;
	int	rx_chain_tail;
	enum status	rx_chain_status;

	int	tx_next_done;
	int	tx_chain_head;
	int	tx_chain_tail;
	enum status	tx_chain_status;
	int tx_count;								/* current # of pkts waiting to be sent */
	int	tx_full;

	struct timer_list    mii_phy_timer;
	unsigned long duplex_mode;

	int   	rx_irq;
	int    tx_irq;
	int    ovr_irq;
	int    und_irq;

	struct net_device_stats stats;
	spinlock_t lock; 							/* Serialise access to device */

	/* debug /proc entry */
	struct proc_dir_entry *ps;
	int dma_halt_cnt;    u32 halt_tx_count;
	int dma_collide_cnt; u32 collide_tx_count;
	int dma_run_cnt;     u32 run_tx_count;
	int dma_race_cnt;    u32 race_tx_count;
	
};

static inline void rc32438_abort_dma(struct net_device *dev, DMA_Chan_t ch)
{
	
	if (local_readl(&ch->dmac) & DMAC_run_m) 
	{
		local_writel(0x10, &ch->dmac); 
		while (!(local_readl(&ch->dmas) & DMAS_h_m))
			dev->trans_start = jiffies;		
		
		local_writel(0, &ch->dmas);  
	}

	local_writel(0, &ch->dmadptr); 
	local_writel(0, &ch->dmandptr); 

}

#endif /* ACACIA_H */