ar531x.h

atheros ar531x gpio driver

 *   - No read or write buffers are included.
 */
#define AR5315_MEM_CFG          (AR5315_SDRAMCTL + 0x00)
#define AR5315_MEM_CTRL         (AR5315_SDRAMCTL + 0x0c)
#define AR5315_MEM_REF          (AR5315_SDRAMCTL + 0x10)

#define SDRAM_DATA_WIDTH_M          0x00006000
#define SDRAM_DATA_WIDTH_S          13

#define SDRAM_COL_WIDTH_M           0x00001E00
#define SDRAM_COL_WIDTH_S           9

#define SDRAM_ROW_WIDTH_M           0x000001E0
#define SDRAM_ROW_WIDTH_S           5

#define SDRAM_BANKADDR_BITS_M       0x00000018
#define SDRAM_BANKADDR_BITS_S       3


/*
 * SDRAM Memory Refresh (MEM_REF) value is computed as:
 * MEMCTL_SREFR = (Tr * hclk_freq) / R
 * where Tr is max. time of refresh of any single row
 * R is number of rows in the DRAM
 * For most 133MHz SDRAM parts, Tr=64ms, R=4096 or 8192
 */
#if defined(COBRA_EMUL)
#define AR5315_SDRAM_MEMORY_REFRESH_VALUE  0x96
#else 
#if defined(DEFAULT_PLL)
#define AR5315_SDRAM_MEMORY_REFRESH_VALUE  0x200
#else
#define AR5315_SDRAM_MEMORY_REFRESH_VALUE  0x61a
#endif /* ! DEFAULT_PLL */
#endif 

#if defined(AR5315)

#define AR5315_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
#define AR5315_SDRAM_DATA_WIDTH     16  /* bits */   
#define AR5315_SDRAM_COL_WIDTH      8
#define AR5315_SDRAM_ROW_WIDTH      12

#else

#define AR5315_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
#define AR5315_SDRAM_DATA_WIDTH     16
#define AR5315_SDRAM_COL_WIDTH      8
#define AR5315_SDRAM_ROW_WIDTH      12

#endif /* ! AR5315 */

/*
 * SPI Flash Interface Registers
 */

#define AR5315_SPI_CTL      (AR5315_SPI + 0x00)
#define AR5315_SPI_OPCODE   (AR5315_SPI + 0x04)
#define AR5315_SPI_DATA     (AR5315_SPI + 0x08)

#define SPI_CTL_START           0x00000100
#define SPI_CTL_BUSY            0x00010000
#define SPI_CTL_TXCNT_MASK      0x0000000f
#define SPI_CTL_RXCNT_MASK      0x000000f0
#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
#define SPI_CTL_SIZE_MASK       0x00060000

#define SPI_CTL_CLK_SEL_MASK    0x03000000
#define SPI_OPCODE_MASK         0x000000ff

/* 
 * PCI-MAC Configuration registers 
 */
#define PCI_MAC_RC              (AR5315_PCI + 0x4000) 
#define PCI_MAC_SCR             (AR5315_PCI + 0x4004)
#define PCI_MAC_INTPEND         (AR5315_PCI + 0x4008)
#define PCI_MAC_SFR             (AR5315_PCI + 0x400C)
#define PCI_MAC_PCICFG          (AR5315_PCI + 0x4010)
#define PCI_MAC_SREV            (AR5315_PCI + 0x4020)

#define PCI_MAC_RC_MAC          0x00000001
#define PCI_MAC_RC_BB           0x00000002

#define PCI_MAC_SCR_SLMODE_M    0x00030000
#define PCI_MAC_SCR_SLMODE_S    16        
#define PCI_MAC_SCR_SLM_FWAKE   0         
#define PCI_MAC_SCR_SLM_FSLEEP  1         
#define PCI_MAC_SCR_SLM_NORMAL  2         

#define PCI_MAC_SFR_SLEEP       0x00000001

#define PCI_MAC_PCICFG_SPWR_DN  0x00010000

 


/*
 * PCI Bus Interface Registers
 */
#define AR5315_PCI_1MS_REG      (AR5315_PCI + 0x0008)
#define AR5315_PCI_1MS_MASK     0x3FFFF         /* # of AHB clk cycles in 1ms */

#define AR5315_PCI_MISC_CONFIG  (AR5315_PCI + 0x000c)
#define AR5315_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
#define AR5315_PCIMISC_CFG_SEL  0x00000002      /* mem or config cycles */
#define AR5315_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
#define AR5315_PCIMISC_RST_MODE 0x00000030
#define AR5315_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
#define AR5315_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
#define AR5315_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
#define AR5315_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
#define AR5315_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
#define AR5315_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
#define AR5315_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */
#define AR5315_PCICACHE_DIS     0x00001000      /* PCI external access cache disable */

#define AR5315_PCI_OUT_TSTAMP   (AR5315_PCI + 0x0010)

#define AR5315_PCI_UNCACHE_CFG  (AR5315_PCI + 0x0014)

#define AR5315_PCI_IN_EN        (AR5315_PCI + 0x0100)
#define AR5315_PCI_IN_EN0       0x01            /* Enable chain 0 */
#define AR5315_PCI_IN_EN1       0x02            /* Enable chain 1 */
#define AR5315_PCI_IN_EN2       0x04            /* Enable chain 2 */
#define AR5315_PCI_IN_EN3       0x08            /* Enable chain 3 */

#define AR5315_PCI_IN_DIS       (AR5315_PCI + 0x0104)
#define AR5315_PCI_IN_DIS0      0x01            /* Disable chain 0 */
#define AR5315_PCI_IN_DIS1      0x02            /* Disable chain 1 */
#define AR5315_PCI_IN_DIS2      0x04            /* Disable chain 2 */
#define AR5315_PCI_IN_DIS3      0x08            /* Disable chain 3 */

#define AR5315_PCI_IN_PTR       (AR5315_PCI + 0x0200)

#define AR5315_PCI_OUT_EN       (AR5315_PCI + 0x0400)
#define AR5315_PCI_OUT_EN0      0x01            /* Enable chain 0 */

#define AR5315_PCI_OUT_DIS      (AR5315_PCI + 0x0404)
#define AR5315_PCI_OUT_DIS0     0x01            /* Disable chain 0 */

#define AR5315_PCI_OUT_PTR      (AR5315_PCI + 0x0408)

#define AR5315_PCI_INT_STATUS   (AR5315_PCI + 0x0500)   /* write one to clr */
#define AR5315_PCI_TXINT        0x00000001      /* Desc In Completed */
#define AR5315_PCI_TXOK         0x00000002      /* Desc In OK */
#define AR5315_PCI_TXERR        0x00000004      /* Desc In ERR */
#define AR5315_PCI_TXEOL        0x00000008      /* Desc In End-of-List */
#define AR5315_PCI_RXINT        0x00000010      /* Desc Out Completed */
#define AR5315_PCI_RXOK         0x00000020      /* Desc Out OK */
#define AR5315_PCI_RXERR        0x00000040      /* Desc Out ERR */
#define AR5315_PCI_RXEOL        0x00000080      /* Desc Out EOL */
#define AR5315_PCI_TXOOD        0x00000200      /* Desc In Out-of-Desc */
#define AR5315_PCI_MASK         0x0000FFFF      /* Desc Mask */
#define AR5315_PCI_EXT_INT      0x02000000      
#define AR5315_PCI_ABORT_INT    0x04000000      

#define AR5315_PCI_INT_MASK     (AR5315_PCI + 0x0504)   /* same as INT_STATUS */

#define AR5315_PCI_INTEN_REG    (AR5315_PCI + 0x0508)
#define AR5315_PCI_INT_DISABLE  0x00            /* disable pci interrupts */
#define AR5315_PCI_INT_ENABLE   0x01            /* enable pci interrupts */

#define AR5315_PCI_HOST_IN_EN   (AR5315_PCI + 0x0800)
#define AR5315_PCI_HOST_IN_DIS  (AR5315_PCI + 0x0804)
#define AR5315_PCI_HOST_IN_PTR  (AR5315_PCI + 0x0810)
#define AR5315_PCI_HOST_OUT_EN  (AR5315_PCI + 0x0900)
#define AR5315_PCI_HOST_OUT_DIS (AR5315_PCI + 0x0904)
#define AR5315_PCI_HOST_OUT_PTR (AR5315_PCI + 0x0908)


/*
 * Local Bus Interface Registers
 */
#define AR5315_LB_CONFIG        (AR5315_LOCAL + 0x0000)
#define AR5315_LBCONF_OE        0x00000001      /* =1 OE is low-true */
#define AR5315_LBCONF_CS0       0x00000002      /* =1 first CS is low-true */
#define AR5315_LBCONF_CS1       0x00000004      /* =1 2nd CS is low-true */
#define AR5315_LBCONF_RDY       0x00000008      /* =1 RDY is low-true */
#define AR5315_LBCONF_WE        0x00000010      /* =1 Write En is low-true */
#define AR5315_LBCONF_WAIT      0x00000020      /* =1 WAIT is low-true */
#define AR5315_LBCONF_ADS       0x00000040      /* =1 Adr Strobe is low-true */
#define AR5315_LBCONF_MOT       0x00000080      /* =0 Intel, =1 Motorola */
#define AR5315_LBCONF_8CS       0x00000100      /* =1 8 bits CS, 0= 16bits */
#define AR5315_LBCONF_8DS       0x00000200      /* =1 8 bits Data S, 0=16bits */
#define AR5315_LBCONF_ADS_EN    0x00000400      /* =1 Enable ADS */
#define AR5315_LBCONF_ADR_OE    0x00000800      /* =1 Adr cap on OE, WE or DS */
#define AR5315_LBCONF_ADDT_MUX  0x00001000      /* =1 Adr and Data share bus */
#define AR5315_LBCONF_DATA_OE   0x00002000      /* =1 Data cap on OE, WE, DS */
#define AR5315_LBCONF_16DATA    0x00004000      /* =1 Data is 16 bits wide */
#define AR5315_LBCONF_SWAPDT    0x00008000      /* =1 Byte swap data */
#define AR5315_LBCONF_SYNC      0x00010000      /* =1 Bus synchronous to clk */
#define AR5315_LBCONF_INT       0x00020000      /* =1 Intr is low true */
#define AR5315_LBCONF_INT_CTR0  0x00000000      /* GND high-Z, Vdd is high-Z */
#define AR5315_LBCONF_INT_CTR1  0x00040000      /* GND drive, Vdd is high-Z */
#define AR5315_LBCONF_INT_CTR2  0x00080000      /* GND high-Z, Vdd drive */
#define AR5315_LBCONF_INT_CTR3  0x000C0000      /* GND drive, Vdd drive */
#define AR5315_LBCONF_RDY_WAIT  0x00100000      /* =1 RDY is negative of WAIT */
#define AR5315_LBCONF_INT_PULSE 0x00200000      /* =1 Interrupt is a pulse */
#define AR5315_LBCONF_ENABLE    0x00400000      /* =1 Falcon respond to LB */

#define AR5315_LB_CLKSEL        (AR5315_LOCAL + 0x0004)
#define AR5315_LBCLK_EXT        0x0001          /* use external clk for lb */

#define AR5315_LB_1MS           (AR5315_LOCAL + 0x0008)
#define AR5315_LB1MS_MASK       0x3FFFF         /* # of AHB clk cycles in 1ms */

#define AR5315_LB_MISCCFG       (AR5315_LOCAL + 0x000C)
#define AR5315_LBM_TXD_EN       0x00000001      /* Enable TXD for fragments */
#define AR5315_LBM_RX_INTEN     0x00000002      /* Enable LB ints on RX ready */
#define AR5315_LBM_MBOXWR_INTEN 0x00000004      /* Enable LB ints on mbox wr */
#define AR5315_LBM_MBOXRD_INTEN 0x00000008      /* Enable LB ints on mbox rd */
#define AR5315_LMB_DESCSWAP_EN  0x00000010      /* Byte swap desc enable */
#define AR5315_LBM_TIMEOUT_MASK 0x00FFFF80
#define AR5315_LBM_TIMEOUT_SHFT 7
#define AR5315_LBM_PORTMUX      0x07000000


#define AR5315_LB_RXTSOFF       (AR5315_LOCAL + 0x0010)

#define AR5315_LB_TX_CHAIN_EN   (AR5315_LOCAL + 0x0100)
#define AR5315_LB_TXEN_0        0x01
#define AR5315_LB_TXEN_1        0x02
#define AR5315_LB_TXEN_2        0x04
#define AR5315_LB_TXEN_3        0x08

#define AR5315_LB_TX_CHAIN_DIS  (AR5315_LOCAL + 0x0104)
#define AR5315_LB_TX_DESC_PTR   (AR5315_LOCAL + 0x0200)

#define AR5315_LB_RX_CHAIN_EN   (AR5315_LOCAL + 0x0400)
#define AR5315_LB_RXEN          0x01

#define AR5315_LB_RX_CHAIN_DIS  (AR5315_LOCAL + 0x0404)
#define AR5315_LB_RX_DESC_PTR   (AR5315_LOCAL + 0x0408)

#define AR5315_LB_INT_STATUS    (AR5315_LOCAL + 0x0500)
#define AR5315_INT_TX_DESC      0x0001
#define AR5315_INT_TX_OK        0x0002
#define AR5315_INT_TX_ERR       0x0004
#define AR5315_INT_TX_EOF       0x0008
#define AR5315_INT_RX_DESC      0x0010
#define AR5315_INT_RX_OK        0x0020
#define AR5315_INT_RX_ERR       0x0040
#define AR5315_INT_RX_EOF       0x0080
#define AR5315_INT_TX_TRUNC     0x0100
#define AR5315_INT_TX_STARVE    0x0200
#define AR5315_INT_LB_TIMEOUT   0x0400
#define AR5315_INT_LB_ERR       0x0800
#define AR5315_INT_MBOX_WR      0x1000
#define AR5315_INT_MBOX_RD      0x2000

/* Bit definitions for INT MASK are the same as INT_STATUS */
#define AR5315_LB_INT_MASK      (AR5315_LOCAL + 0x0504)

#define AR5315_LB_INT_EN        (AR5315_LOCAL + 0x0508)
#define AR5315_LB_MBOX          (AR5315_LOCAL + 0x0600)



/*
 * IR Interface Registers
 */
#define AR5315_IR_PKTDATA                   (AR5315_IR + 0x0000)

#define AR5315_IR_PKTLEN                    (AR5315_IR + 0x07fc) /* 0 - 63 */

#define AR5315_IR_CONTROL                   (AR5315_IR + 0x0800)
#define AR5315_IRCTL_TX                     0x00000000  /* use as tranmitter */
#define AR5315_IRCTL_RX                     0x00000001  /* use as receiver   */
#define AR5315_IRCTL_SAMPLECLK_MASK         0x00003ffe  /* Sample clk divisor mask */
#define AR5315_IRCTL_SAMPLECLK_SHFT                  1
#define AR5315_IRCTL_OUTPUTCLK_MASK         0x03ffc000  /* Output clk divisor mask */
#define AR5315_IRCTL_OUTPUTCLK_SHFT                 14

#define AR5315_IR_STATUS                    (AR5315_IR + 0x0804)
#define AR5315_IRSTS_RX                     0x00000001  /* receive in progress */
#define AR5315_IRSTS_TX                     0x00000002  /* transmit in progress */

#define AR5315_IR_CONFIG                    (AR5315_IR + 0x0808)
#define AR5315_IRCFG_INVIN                  0x00000001  /* invert input polarity */
#define AR5315_IRCFG_INVOUT                 0x00000002  /* invert output polarity */
#define AR5315_IRCFG_SEQ_START_WIN_SEL      0x00000004  /* 1 => 28, 0 => 7 */
#define AR5315_IRCFG_SEQ_START_THRESH       0x000000f0  /*  */
#define AR5315_IRCFG_SEQ_END_UNIT_SEL       0x00000100  /*  */
#define AR5315_IRCFG_SEQ_END_UNIT_THRESH    0x00007e00  /*  */
#define AR5315_IRCFG_SEQ_END_WIN_SEL        0x00008000  /*  */
#define AR5315_IRCFG_SEQ_END_WIN_THRESH     0x001f0000  /*  */
#define AR5315_IRCFG_NUM_BACKOFF_WORDS      0x01e00000  /*  */

/*
 * PCI memory constants: Memory area 1 and 2 are the same size -
 * (twice the PCI_TLB_PAGE_SIZE). The definition of
 * CPU_TO_PCI_MEM_SIZE is coupled with the TLB setup routine
 * sysLib.c/sysTlbInit(), in that it assumes that 2 pages of size
 * PCI_TLB_PAGE_SIZE are set up in the TLB for each PCI memory space.
 */
 
#define CPU_TO_PCI_MEM_BASE1    0xE0000000
#define CPU_TO_PCI_MEM_SIZE1    (2*PCI_TLB_PAGE_SIZE)
 

/* TLB attributes for PCI transactions */

#define PCI_MMU_PAGEMASK        0x00003FFF
#define MMU_PAGE_UNCACHED       0x00000010
#define MMU_PAGE_DIRTY          0x00000004
#define MMU_PAGE_VALID          0x00000002
#define MMU_PAGE_GLOBAL         0x00000001
#define PCI_MMU_PAGEATTRIB      (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\
                                 MMU_PAGE_VALID|MMU_PAGE_GLOBAL)
#define PCI_MEMORY_SPACE1_VIRT  0xE0000000      /* Used for non-prefet  mem   */
#define PCI_MEMORY_SPACE1_PHYS  0x80000000
#define PCI_TLB_PAGE_SIZE       0x01000000
#define TLB_HI_MASK             0xFFFFE000
#define TLB_LO_MASK             0x3FFFFFFF
#define PAGEMASK_SHIFT          11
#define TLB_LO_SHIFT            6

#define PCI_MAX_LATENCY         0xFFF           /* Max PCI latency            */

#define HOST_PCI_DEV_ID         3
#define HOST_PCI_MBAR0          0x10000000
#define HOST_PCI_MBAR1          0x20000000
#define HOST_PCI_MBAR2          0x30000000

#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
#define PCI_DEVICE_MEM_SPACE    0x800000


typedef unsigned int AR531X_REG;

#define sysRegRead(phys)	\
	(*(volatile AR531X_REG *)PHYS_TO_K1(phys))

#define sysRegWrite(phys, val)	\
	((*(volatile AR531X_REG *)PHYS_TO_K1(phys)) = (val))
#endif

#endif