ar531x.h

atheros ar531x gpio driver

#define ARB_WLAN                    0x00000002      /* WLAN */
#define ARB_MPEGTS_RSVD             0x00000004      /* MPEG-TS */
#define ARB_LOCAL                   0x00000008      /* LOCAL */
#define ARB_PCI                     0x00000010      /* PCI */
#define ARB_ETHERNET                0x00000020      /* Ethernet */
#define ARB_RETRY                   0x00000100      /* retry policy, debug only */

/*
 * Config Register
 */
#define AR5315_ENDIAN_CTL       (AR5315_DSLBASE + 0x000c)

#define CONFIG_AHB                  0x00000001      /* EC - AHB bridge endianess */
#define CONFIG_WLAN                 0x00000002      /* WLAN byteswap */
#define CONFIG_MPEGTS_RSVD          0x00000004      /* MPEG-TS byteswap */
#define CONFIG_PCI                  0x00000008      /* PCI byteswap */
#define CONFIG_MEMCTL               0x00000010      /* Memory controller endianess */
#define CONFIG_LOCAL                0x00000020      /* Local bus byteswap */
#define CONFIG_ETHERNET             0x00000040      /* Ethernet byteswap */

#define CONFIG_MERGE                0x00000200      /* CPU write buffer merge */
#define CONFIG_CPU                  0x00000400      /* CPU big endian */
#define CONFIG_PCIAHB               0x00000800
#define CONFIG_PCIAHB_BRIDGE        0x00001000
#define CONFIG_SPI                  0x00008000      /* SPI byteswap */
#define CONFIG_CPU_DRAM             0x00010000
#define CONFIG_CPU_PCI              0x00020000
#define CONFIG_CPU_MMR              0x00040000
#define CONFIG_BIG                  0x00000400      


/*
 * NMI control
 */
#define AR5315_NMI_CTL          (AR5315_DSLBASE + 0x0010)

#define NMI_EN  1

/*
 * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
 */
#define AR5315_SREV             (AR5315_DSLBASE + 0x0014)

#define REV_MAJ                     0x00f0
#define REV_MAJ_S                   4
#define REV_MIN                     0x000f
#define REV_MIN_S                   0
#define REV_CHIP                    (REV_MAJ|REV_MIN)

/*
 * Interface Enable
 */
#define AR5315_IF_CTL           (AR5315_DSLBASE + 0x0018)

#define IF_MASK                     0x00000007
#define IF_DISABLED                 0
#define IF_PCI                      1
#define IF_TS_LOCAL                 2
#define IF_ALL                      3   /* only for emulation with separate pins */
#define IF_LOCAL_HOST               0x00000008
#define IF_PCI_HOST                 0x00000010
#define IF_PCI_INTR                 0x00000020
#define IF_PCI_CLK_MASK             0x00030000
#define IF_PCI_CLK_INPUT            0 
#define IF_PCI_CLK_OUTPUT_LOW       1
#define IF_PCI_CLK_OUTPUT_CLK       2
#define IF_PCI_CLK_OUTPUT_HIGH      3
#define IF_PCI_CLK_SHIFT            16 
 
                
/* Major revision numbers, bits 7..4 of Revision ID register */
#define REV_MAJ_AR5311              0x01
#define REV_MAJ_AR5312              0x04
#define REV_MAJ_AR5315              0x0B

/*
 * APB Interrupt control
 */

#define AR5315_ISR              (AR5315_DSLBASE + 0x0020)
#define AR5315_IMR              (AR5315_DSLBASE + 0x0024)
#define AR5315_GISR             (AR5315_DSLBASE + 0x0028)

#define ISR_UART0                   0x0001           /* high speed UART */
#define ISR_I2C_RSVD                0x0002           /* I2C bus */
#define ISR_SPI                     0x0004           /* SPI bus */
#define ISR_AHB                     0x0008           /* AHB error */
#define ISR_APB                     0x0010           /* APB error */
#define ISR_TIMER                   0x0020           /* timer */
#define ISR_GPIO                    0x0040           /* GPIO */
#define ISR_WD                      0x0080           /* watchdog */
#define ISR_IR_RSVD                 0x0100           /* IR */
                                
#define IMR_UART0                   ISR_UART0
#define IMR_I2C_RSVD                ISR_I2C_RSVD
#define IMR_SPI                     ISR_SPI
#define IMR_AHB                     ISR_AHB
#define IMR_APB                     ISR_APB
#define IMR_TIMER                   ISR_TIMER
#define IMR_GPIO                    ISR_GPIO
#define IMR_WD                      ISR_WD
#define IMR_IR_RSVD                 ISR_IR_RSVD

#define GISR_MISC                   0x0001
#define GISR_WLAN0                  0x0002
#define GISR_MPEGTS_RSVD            0x0004
#define GISR_LOCALPCI               0x0008
#define GISR_WMACPOLL               0x0010
#define GISR_TIMER                  0x0020
#define GISR_ETHERNET               0x0040

/*
 * Interrupt routing from IO to the processor IP bits
 * Define our inter mask and level
 */
#define AR5315_INTR_MISCIO      SR_IBIT3
#define AR5315_INTR_WLAN0       SR_IBIT4
#define AR5315_INTR_ENET0       SR_IBIT5
#define AR5315_INTR_LOCALPCI    SR_IBIT6
#define AR5315_INTR_WMACPOLL    SR_IBIT7
#define AR5315_INTR_COMPARE     SR_IBIT8

/*
 * Timers
 */
#define AR5315_TIMER            (AR5315_DSLBASE + 0x0030)
#define AR5315_RELOAD           (AR5315_DSLBASE + 0x0034)
#define AR5315_WD               (AR5315_DSLBASE + 0x0038)
#define AR5315_WDC              (AR5315_DSLBASE + 0x003c)

#define WDC_RESET                   0x00000002               /* reset on watchdog */
#define WDC_NMI                     0x00000001               /* NMI on watchdog */
#define WDC_IGNORE_EXPIRATION       0x00000000

/*
 * Interface Debug
 */
#define AR531X_FLASHDBG             (AR531X_RESETTMR + 0x0040)
#define AR531X_MIIDBG               (AR531X_RESETTMR + 0x0044)


/*
 * CPU Performance Counters
 */
#define AR5315_PERFCNT0         (AR5315_DSLBASE + 0x0048)
#define AR5315_PERFCNT1         (AR5315_DSLBASE + 0x004c)

#define PERF_DATAHIT                0x0001  /* Count Data Cache Hits */
#define PERF_DATAMISS               0x0002  /* Count Data Cache Misses */
#define PERF_INSTHIT                0x0004  /* Count Instruction Cache Hits */
#define PERF_INSTMISS               0x0008  /* Count Instruction Cache Misses */
#define PERF_ACTIVE                 0x0010  /* Count Active Processor Cycles */
#define PERF_WBHIT                  0x0020  /* Count CPU Write Buffer Hits */
#define PERF_WBMISS                 0x0040  /* Count CPU Write Buffer Misses */
                                
#define PERF_EB_ARDY                0x0001  /* Count EB_ARdy signal */
#define PERF_EB_AVALID              0x0002  /* Count EB_AValid signal */
#define PERF_EB_WDRDY               0x0004  /* Count EB_WDRdy signal */
#define PERF_EB_RDVAL               0x0008  /* Count EB_RdVal signal */
#define PERF_VRADDR                 0x0010  /* Count valid read address cycles */
#define PERF_VWADDR                 0x0020  /* Count valid write address cycles */
#define PERF_VWDATA                 0x0040  /* Count valid write data cycles */

/*
 * AHB Error Reporting.
 */
#define AR5315_AHB_ERR0         (AR5315_DSLBASE + 0x0050)  /* error  */
#define AR5315_AHB_ERR1         (AR5315_DSLBASE + 0x0054)  /* haddr  */
#define AR5315_AHB_ERR2         (AR5315_DSLBASE + 0x0058)  /* hwdata */
#define AR5315_AHB_ERR3         (AR5315_DSLBASE + 0x005c)  /* hrdata */
#define AR5315_AHB_ERR4         (AR5315_DSLBASE + 0x0060)  /* status */

#define AHB_ERROR_DET               1   /* AHB Error has been detected,          */
                                        /* write 1 to clear all bits in ERR0     */
#define AHB_ERROR_OVR               2   /* AHB Error overflow has been detected  */
#define AHB_ERROR_WDT               4   /* AHB Error due to wdt instead of hresp */

#define PROCERR_HMAST               0x0000000f
#define PROCERR_HMAST_DFLT          0
#define PROCERR_HMAST_WMAC          1
#define PROCERR_HMAST_ENET          2
#define PROCERR_HMAST_PCIENDPT      3
#define PROCERR_HMAST_LOCAL         4
#define PROCERR_HMAST_CPU           5
#define PROCERR_HMAST_PCITGT        6
                                    
#define PROCERR_HMAST_S             0
#define PROCERR_HWRITE              0x00000010
#define PROCERR_HSIZE               0x00000060
#define PROCERR_HSIZE_S             5
#define PROCERR_HTRANS              0x00000180
#define PROCERR_HTRANS_S            7
#define PROCERR_HBURST              0x00000e00
#define PROCERR_HBURST_S            9



/*
 * Clock Control
 */
#define AR5315_PLLC_CTL         (AR5315_DSLBASE + 0x0064)
#define AR5315_PLLV_CTL         (AR5315_DSLBASE + 0x0068)
#define AR5315_CPUCLK           (AR5315_DSLBASE + 0x006c)
#define AR5315_AMBACLK          (AR5315_DSLBASE + 0x0070)
#define AR5315_SYNCCLK          (AR5315_DSLBASE + 0x0074)
#define AR5315_DSL_SLEEP_CTL    (AR5315_DSLBASE + 0x0080)
#define AR5315_DSL_SLEEP_DUR    (AR5315_DSLBASE + 0x0084)

/* PLLc Control fields */
#define PLLC_REF_DIV_M              0x00000003
#define PLLC_REF_DIV_S              0
#define PLLC_FDBACK_DIV_M           0x0000007C
#define PLLC_FDBACK_DIV_S           2
#define PLLC_ADD_FDBACK_DIV_M       0x00000080
#define PLLC_ADD_FDBACK_DIV_S       7
#define PLLC_CLKC_DIV_M             0x0001c000
#define PLLC_CLKC_DIV_S             14
#define PLLC_CLKM_DIV_M             0x00700000
#define PLLC_CLKM_DIV_S             20

/* CPU CLK Control fields */
#define CPUCLK_CLK_SEL_M            0x00000003
#define CPUCLK_CLK_SEL_S            0
#define CPUCLK_CLK_DIV_M            0x0000000c
#define CPUCLK_CLK_DIV_S            2

/* AMBA CLK Control fields */
#define AMBACLK_CLK_SEL_M           0x00000003
#define AMBACLK_CLK_SEL_S           0
#define AMBACLK_CLK_DIV_M           0x0000000c
#define AMBACLK_CLK_DIV_S           2

#if defined(COBRA_EMUL)
#define AR5315_AMBA_CLOCK_RATE  20000000
#define AR5315_CPU_CLOCK_RATE   40000000
#else
#if defined(DEFAULT_PLL)
#define AR5315_AMBA_CLOCK_RATE  40000000
#define AR5315_CPU_CLOCK_RATE   40000000
#else
#define AR5315_AMBA_CLOCK_RATE  92000000
#define AR5315_CPU_CLOCK_RATE   184000000
#endif /* ! DEFAULT_PLL */
#endif /* ! COBRA_EMUL */

#define AR5315_UART_CLOCK_RATE  AR5315_AMBA_CLOCK_RATE
#define AR5315_SDRAM_CLOCK_RATE AR5315_AMBA_CLOCK_RATE

/*
 * The UART computes baud rate as:
 *   baud = clock / (16 * divisor)
 * where divisor is specified as a High Byte (DLM) and a Low Byte (DLL).
 */
#define DESIRED_BAUD_RATE           38400

/*
 * The WATCHDOG value is computed as
 *  10 seconds * AR531X_WATCHDOG_CLOCK_RATE
 */
#define DESIRED_WATCHDOG_SECONDS    10
#define AR531X_WATCHDOG_TIME \
        (DESIRED_WATCHDOG_SECONDS * AR531X_WATCHDOG_CLOCK_RATE)


#define CLOCKCTL_UART0  0x0010  /* enable UART0 external clock */


 /*
 * Applicable "PCICFG" bits for WLAN(s).  Assoc status and LED mode.
 */
#define AR531X_PCICFG               (AR531X_RESETTMR + 0x00b0)
#define ASSOC_STATUS_M              0x00000003
#define ASSOC_STATUS_NONE           0
#define ASSOC_STATUS_PENDING        1   
#define ASSOC_STATUS_ASSOCIATED     2
#define LED_MODE_M                  0x0000001c
#define LED_BLINK_THRESHOLD_M       0x000000e0
#define LED_SLOW_BLINK_MODE         0x00000100

/*
 * GPIO
 */

#define AR5315_GPIO_DI          (AR5315_DSLBASE + 0x0088)
#define AR5315_GPIO_DO          (AR5315_DSLBASE + 0x0090)
#define AR5315_GPIO_CR          (AR5315_DSLBASE + 0x0098)
#define AR5315_GPIO_INT         (AR5315_DSLBASE + 0x00a0)

#define GPIO_CR_M(x)                (1 << (x))                  /* mask for i/o */
#define GPIO_CR_O(x)                (1 << (x))                  /* output */
#define GPIO_CR_I(x)                (0 << (x))                  /* input */

#define GPIO_INT(x,Y)               ((x) << (8 * (Y)))          /* interrupt enable */
#define GPIO_INT_M(Y)               ((0x3F) << (8 * (Y)))       /* mask for int */
#define GPIO_INT_LVL(x,Y)           ((x) << (8 * (Y) + 6))      /* interrupt level */
#define GPIO_INT_LVL_M(Y)           ((0x3) << (8 * (Y) + 6))    /* mask for int level */

#define AR5315_RESET_GPIO       5
#define AR5315_NUM_GPIO         22

    
/* 
 *  PCI Clock Control
 */     
 
#define AR5315_PCICLK           (AR5315_DSLBASE + 0x00a4)

#define PCICLK_INPUT_M              0x3
#define PCICLK_INPUT_S              0
                         
#define PCICLK_PLLC_CLKM            0
#define PCICLK_PLLC_CLKM1           1
#define PCICLK_PLLC_CLKC            2
#define PCICLK_REF_CLK              3 

#define PCICLK_DIV_M                0xc
#define PCICLK_DIV_S                2
                         
#define PCICLK_IN_FREQ              0
#define PCICLK_IN_FREQ_DIV_6        1
#define PCICLK_IN_FREQ_DIV_8        2
#define PCICLK_IN_FREQ_DIV_10       3 

/*
 * Observation Control Register
 */
#define AR5315_OCR              (AR5315_DSLBASE + 0x00b0)
#define OCR_GPIO0_IRIN              0x0040
#define OCR_GPIO1_IROUT             0x0080
#define OCR_GPIO3_RXCLR             0x0200

/* 
 *  General Clock Control
 */     
 
#define AR5315_MISCCLK          (AR5315_DSLBASE + 0x00b4)
#define MISCCLK_PLLBYPASS_EN        0x00000001
#define MISCCLK_PROCREFCLK          0x00000002

/*
 * SDRAM Controller