ar531x.h

atheros ar531x watchdog driver

#define AR531XPLUS_PCICACHE_DIS     0x00001000      /* PCI external access cache disable */

#define AR531XPLUS_PCI_OUT_TSTAMP   (AR531XPLUS_PCI + 0x0010)

#define AR531XPLUS_PCI_UNCACHE_CFG  (AR531XPLUS_PCI + 0x0014)

#define AR531XPLUS_PCI_IN_EN        (AR531XPLUS_PCI + 0x0100)
#define AR531XPLUS_PCI_IN_EN0       0x01            /* Enable chain 0 */
#define AR531XPLUS_PCI_IN_EN1       0x02            /* Enable chain 1 */
#define AR531XPLUS_PCI_IN_EN2       0x04            /* Enable chain 2 */
#define AR531XPLUS_PCI_IN_EN3       0x08            /* Enable chain 3 */

#define AR531XPLUS_PCI_IN_DIS       (AR531XPLUS_PCI + 0x0104)
#define AR531XPLUS_PCI_IN_DIS0      0x01            /* Disable chain 0 */
#define AR531XPLUS_PCI_IN_DIS1      0x02            /* Disable chain 1 */
#define AR531XPLUS_PCI_IN_DIS2      0x04            /* Disable chain 2 */
#define AR531XPLUS_PCI_IN_DIS3      0x08            /* Disable chain 3 */

#define AR531XPLUS_PCI_IN_PTR       (AR531XPLUS_PCI + 0x0200)

#define AR531XPLUS_PCI_OUT_EN       (AR531XPLUS_PCI + 0x0400)
#define AR531XPLUS_PCI_OUT_EN0      0x01            /* Enable chain 0 */

#define AR531XPLUS_PCI_OUT_DIS      (AR531XPLUS_PCI + 0x0404)
#define AR531XPLUS_PCI_OUT_DIS0     0x01            /* Disable chain 0 */

#define AR531XPLUS_PCI_OUT_PTR      (AR531XPLUS_PCI + 0x0408)

#define AR531XPLUS_PCI_INT_STATUS   (AR531XPLUS_PCI + 0x0500)   /* write one to clr */
#define AR531XPLUS_PCI_TXINT        0x00000001      /* Desc In Completed */
#define AR531XPLUS_PCI_TXOK         0x00000002      /* Desc In OK */
#define AR531XPLUS_PCI_TXERR        0x00000004      /* Desc In ERR */
#define AR531XPLUS_PCI_TXEOL        0x00000008      /* Desc In End-of-List */
#define AR531XPLUS_PCI_RXINT        0x00000010      /* Desc Out Completed */
#define AR531XPLUS_PCI_RXOK         0x00000020      /* Desc Out OK */
#define AR531XPLUS_PCI_RXERR        0x00000040      /* Desc Out ERR */
#define AR531XPLUS_PCI_RXEOL        0x00000080      /* Desc Out EOL */
#define AR531XPLUS_PCI_TXOOD        0x00000200      /* Desc In Out-of-Desc */
#define AR531XPLUS_PCI_MASK         0x0000FFFF      /* Desc Mask */
#define AR531XPLUS_PCI_EXT_INT      0x02000000      
#define AR531XPLUS_PCI_ABORT_INT    0x04000000      

#define AR531XPLUS_PCI_INT_MASK     (AR531XPLUS_PCI + 0x0504)   /* same as INT_STATUS */

#define AR531XPLUS_PCI_INTEN_REG    (AR531XPLUS_PCI + 0x0508)
#define AR531XPLUS_PCI_INT_DISABLE  0x00            /* disable pci interrupts */
#define AR531XPLUS_PCI_INT_ENABLE   0x01            /* enable pci interrupts */

#define AR531XPLUS_PCI_HOST_IN_EN   (AR531XPLUS_PCI + 0x0800)
#define AR531XPLUS_PCI_HOST_IN_DIS  (AR531XPLUS_PCI + 0x0804)
#define AR531XPLUS_PCI_HOST_IN_PTR  (AR531XPLUS_PCI + 0x0810)
#define AR531XPLUS_PCI_HOST_OUT_EN  (AR531XPLUS_PCI + 0x0900)
#define AR531XPLUS_PCI_HOST_OUT_DIS (AR531XPLUS_PCI + 0x0904)
#define AR531XPLUS_PCI_HOST_OUT_PTR (AR531XPLUS_PCI + 0x0908)


/*
 * Local Bus Interface Registers
 */
#define AR531XPLUS_LB_CONFIG        (AR531XPLUS_LOCAL + 0x0000)
#define AR531XPLUS_LBCONF_OE        0x00000001      /* =1 OE is low-true */
#define AR531XPLUS_LBCONF_CS0       0x00000002      /* =1 first CS is low-true */
#define AR531XPLUS_LBCONF_CS1       0x00000004      /* =1 2nd CS is low-true */
#define AR531XPLUS_LBCONF_RDY       0x00000008      /* =1 RDY is low-true */
#define AR531XPLUS_LBCONF_WE        0x00000010      /* =1 Write En is low-true */
#define AR531XPLUS_LBCONF_WAIT      0x00000020      /* =1 WAIT is low-true */
#define AR531XPLUS_LBCONF_ADS       0x00000040      /* =1 Adr Strobe is low-true */
#define AR531XPLUS_LBCONF_MOT       0x00000080      /* =0 Intel, =1 Motorola */
#define AR531XPLUS_LBCONF_8CS       0x00000100      /* =1 8 bits CS, 0= 16bits */
#define AR531XPLUS_LBCONF_8DS       0x00000200      /* =1 8 bits Data S, 0=16bits */
#define AR531XPLUS_LBCONF_ADS_EN    0x00000400      /* =1 Enable ADS */
#define AR531XPLUS_LBCONF_ADR_OE    0x00000800      /* =1 Adr cap on OE, WE or DS */
#define AR531XPLUS_LBCONF_ADDT_MUX  0x00001000      /* =1 Adr and Data share bus */
#define AR531XPLUS_LBCONF_DATA_OE   0x00002000      /* =1 Data cap on OE, WE, DS */
#define AR531XPLUS_LBCONF_16DATA    0x00004000      /* =1 Data is 16 bits wide */
#define AR531XPLUS_LBCONF_SWAPDT    0x00008000      /* =1 Byte swap data */
#define AR531XPLUS_LBCONF_SYNC      0x00010000      /* =1 Bus synchronous to clk */
#define AR531XPLUS_LBCONF_INT       0x00020000      /* =1 Intr is low true */
#define AR531XPLUS_LBCONF_INT_CTR0  0x00000000      /* GND high-Z, Vdd is high-Z */
#define AR531XPLUS_LBCONF_INT_CTR1  0x00040000      /* GND drive, Vdd is high-Z */
#define AR531XPLUS_LBCONF_INT_CTR2  0x00080000      /* GND high-Z, Vdd drive */
#define AR531XPLUS_LBCONF_INT_CTR3  0x000C0000      /* GND drive, Vdd drive */
#define AR531XPLUS_LBCONF_RDY_WAIT  0x00100000      /* =1 RDY is negative of WAIT */
#define AR531XPLUS_LBCONF_INT_PULSE 0x00200000      /* =1 Interrupt is a pulse */
#define AR531XPLUS_LBCONF_ENABLE    0x00400000      /* =1 Falcon respond to LB */

#define AR531XPLUS_LB_CLKSEL        (AR531XPLUS_LOCAL + 0x0004)
#define AR531XPLUS_LBCLK_EXT        0x0001          /* use external clk for lb */

#define AR531XPLUS_LB_1MS           (AR531XPLUS_LOCAL + 0x0008)
#define AR531XPLUS_LB1MS_MASK       0x3FFFF         /* # of AHB clk cycles in 1ms */

#define AR531XPLUS_LB_MISCCFG       (AR531XPLUS_LOCAL + 0x000C)
#define AR531XPLUS_LBM_TXD_EN       0x00000001      /* Enable TXD for fragments */
#define AR531XPLUS_LBM_RX_INTEN     0x00000002      /* Enable LB ints on RX ready */
#define AR531XPLUS_LBM_MBOXWR_INTEN 0x00000004      /* Enable LB ints on mbox wr */
#define AR531XPLUS_LBM_MBOXRD_INTEN 0x00000008      /* Enable LB ints on mbox rd */
#define AR531XPLUS_LMB_DESCSWAP_EN  0x00000010      /* Byte swap desc enable */
#define AR531XPLUS_LBM_TIMEOUT_MASK 0x00FFFF80
#define AR531XPLUS_LBM_TIMEOUT_SHFT 7
#define AR531XPLUS_LBM_PORTMUX      0x07000000


#define AR531XPLUS_LB_RXTSOFF       (AR531XPLUS_LOCAL + 0x0010)

#define AR531XPLUS_LB_TX_CHAIN_EN   (AR531XPLUS_LOCAL + 0x0100)
#define AR531XPLUS_LB_TXEN_0        0x01
#define AR531XPLUS_LB_TXEN_1        0x02
#define AR531XPLUS_LB_TXEN_2        0x04
#define AR531XPLUS_LB_TXEN_3        0x08

#define AR531XPLUS_LB_TX_CHAIN_DIS  (AR531XPLUS_LOCAL + 0x0104)
#define AR531XPLUS_LB_TX_DESC_PTR   (AR531XPLUS_LOCAL + 0x0200)

#define AR531XPLUS_LB_RX_CHAIN_EN   (AR531XPLUS_LOCAL + 0x0400)
#define AR531XPLUS_LB_RXEN          0x01

#define AR531XPLUS_LB_RX_CHAIN_DIS  (AR531XPLUS_LOCAL + 0x0404)
#define AR531XPLUS_LB_RX_DESC_PTR   (AR531XPLUS_LOCAL + 0x0408)

#define AR531XPLUS_LB_INT_STATUS    (AR531XPLUS_LOCAL + 0x0500)
#define AR531XPLUS_INT_TX_DESC      0x0001
#define AR531XPLUS_INT_TX_OK        0x0002
#define AR531XPLUS_INT_TX_ERR       0x0004
#define AR531XPLUS_INT_TX_EOF       0x0008
#define AR531XPLUS_INT_RX_DESC      0x0010
#define AR531XPLUS_INT_RX_OK        0x0020
#define AR531XPLUS_INT_RX_ERR       0x0040
#define AR531XPLUS_INT_RX_EOF       0x0080
#define AR531XPLUS_INT_TX_TRUNC     0x0100
#define AR531XPLUS_INT_TX_STARVE    0x0200
#define AR531XPLUS_INT_LB_TIMEOUT   0x0400
#define AR531XPLUS_INT_LB_ERR       0x0800
#define AR531XPLUS_INT_MBOX_WR      0x1000
#define AR531XPLUS_INT_MBOX_RD      0x2000

/* Bit definitions for INT MASK are the same as INT_STATUS */
#define AR531XPLUS_LB_INT_MASK      (AR531XPLUS_LOCAL + 0x0504)

#define AR531XPLUS_LB_INT_EN        (AR531XPLUS_LOCAL + 0x0508)
#define AR531XPLUS_LB_MBOX          (AR531XPLUS_LOCAL + 0x0600)



/*
 * IR Interface Registers
 */
#define AR531XPLUS_IR_PKTDATA                   (AR531XPLUS_IR + 0x0000)

#define AR531XPLUS_IR_PKTLEN                    (AR531XPLUS_IR + 0x07fc) /* 0 - 63 */

#define AR531XPLUS_IR_CONTROL                   (AR531XPLUS_IR + 0x0800)
#define AR531XPLUS_IRCTL_TX                     0x00000000  /* use as tranmitter */
#define AR531XPLUS_IRCTL_RX                     0x00000001  /* use as receiver   */
#define AR531XPLUS_IRCTL_SAMPLECLK_MASK         0x00003ffe  /* Sample clk divisor mask */
#define AR531XPLUS_IRCTL_SAMPLECLK_SHFT                  1
#define AR531XPLUS_IRCTL_OUTPUTCLK_MASK         0x03ffc000  /* Output clk divisor mask */
#define AR531XPLUS_IRCTL_OUTPUTCLK_SHFT                 14

#define AR531XPLUS_IR_STATUS                    (AR531XPLUS_IR + 0x0804)
#define AR531XPLUS_IRSTS_RX                     0x00000001  /* receive in progress */
#define AR531XPLUS_IRSTS_TX                     0x00000002  /* transmit in progress */

#define AR531XPLUS_IR_CONFIG                    (AR531XPLUS_IR + 0x0808)
#define AR531XPLUS_IRCFG_INVIN                  0x00000001  /* invert input polarity */
#define AR531XPLUS_IRCFG_INVOUT                 0x00000002  /* invert output polarity */
#define AR531XPLUS_IRCFG_SEQ_START_WIN_SEL      0x00000004  /* 1 => 28, 0 => 7 */
#define AR531XPLUS_IRCFG_SEQ_START_THRESH       0x000000f0  /*  */
#define AR531XPLUS_IRCFG_SEQ_END_UNIT_SEL       0x00000100  /*  */
#define AR531XPLUS_IRCFG_SEQ_END_UNIT_THRESH    0x00007e00  /*  */
#define AR531XPLUS_IRCFG_SEQ_END_WIN_SEL        0x00008000  /*  */
#define AR531XPLUS_IRCFG_SEQ_END_WIN_THRESH     0x001f0000  /*  */
#define AR531XPLUS_IRCFG_NUM_BACKOFF_WORDS      0x01e00000  /*  */

/*
 * PCI memory constants: Memory area 1 and 2 are the same size -
 * (twice the PCI_TLB_PAGE_SIZE). The definition of
 * CPU_TO_PCI_MEM_SIZE is coupled with the TLB setup routine
 * sysLib.c/sysTlbInit(), in that it assumes that 2 pages of size
 * PCI_TLB_PAGE_SIZE are set up in the TLB for each PCI memory space.
 */
 
#define CPU_TO_PCI_MEM_BASE1    0xE0000000
#define CPU_TO_PCI_MEM_SIZE1    (2*PCI_TLB_PAGE_SIZE)
 

/* TLB attributes for PCI transactions */

#define PCI_MMU_PAGEMASK        0x00003FFF
#define MMU_PAGE_UNCACHED       0x00000010
#define MMU_PAGE_DIRTY          0x00000004
#define MMU_PAGE_VALID          0x00000002
#define MMU_PAGE_GLOBAL         0x00000001
#define PCI_MMU_PAGEATTRIB      (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\
                                 MMU_PAGE_VALID|MMU_PAGE_GLOBAL)
#define PCI_MEMORY_SPACE1_VIRT  0xE0000000      /* Used for non-prefet  mem   */
#define PCI_MEMORY_SPACE1_PHYS  0x80000000
#define PCI_TLB_PAGE_SIZE       0x01000000
#define TLB_HI_MASK             0xFFFFE000
#define TLB_LO_MASK             0x3FFFFFFF
#define PAGEMASK_SHIFT          11
#define TLB_LO_SHIFT            6

#define PCI_MAX_LATENCY         0xFFF           /* Max PCI latency            */

#define HOST_PCI_DEV_ID         3
#define HOST_PCI_MBAR0          0x10000000
#define HOST_PCI_MBAR1          0x20000000
#define HOST_PCI_MBAR2          0x30000000

#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
#define PCI_DEVICE_MEM_SPACE    0x800000


typedef unsigned int AR531X_REG;

#define sysRegRead(phys)	\
	(*(volatile AR531X_REG *)PHYS_TO_K1(phys))

#define sysRegWrite(phys, val)	\
	((*(volatile AR531X_REG *)PHYS_TO_K1(phys)) = (val))



/*
 * This is board-specific data that is stored in a "fixed" location in flash.
 * It is shared across operating systems, so it should not be changed lightly.
 * The main reason we need it is in order to extract the ethernet MAC
 * address(es).
 */
struct ar531x_boarddata {
    u32 magic;                       /* board data is valid */
#define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
    u16 cksum;                       /* checksum (starting with BD_REV 2) */
    u16 rev;                         /* revision of this struct */
#define BD_REV  4
    char   boardName[64];            /* Name of board */
    u16 major;                       /* Board major number */
    u16 minor;                       /* Board minor number */
    u32 config;                      /* Board configuration */
#define BD_ENET0        0x00000001   /* ENET0 is stuffed */
#define BD_ENET1        0x00000002   /* ENET1 is stuffed */
#define BD_UART1        0x00000004   /* UART1 is stuffed */
#define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
#define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
#define BD_SYSLED       0x00000020   /* System LED stuffed */
#define BD_EXTUARTCLK   0x00000040   /* External UART clock */
#define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
#define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
#define BD_WLAN0        0x00000200   /* Enable WLAN0 */
#define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
#define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
#define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
#define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
#define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
#define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
#define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
#define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
    u16 resetConfigGpio;             /* Reset factory GPIO pin */
    u16 sysLedGpio;                  /* System LED GPIO pin */

    u32 cpuFreq;                     /* CPU core frequency in Hz */
    u32 sysFreq;                     /* System frequency in Hz */
    u32 cntFreq;                     /* Calculated C0_COUNT frequency */

    u8  wlan0Mac[6];
    u8  enet0Mac[6];
    u8  enet1Mac[6];

    u16 pciId;                       /* Pseudo PCIID for common code */
    u16 memCap;                      /* cap bank1 in MB */

    /* version 3 */
    u8  wlan1Mac[6];                 /* (ar5212) */
};

#endif

#endif /* AR531X_H */