ar531x.h

atheros ar531x watchdog driver

                                        /* write 1 to clear all bits in ERR0     */
#define AHB_ERROR_OVR               2   /* AHB Error overflow has been detected  */
#define AHB_ERROR_WDT               4   /* AHB Error due to wdt instead of hresp */

#define PROCERR_HMAST               0x0000000f
#define PROCERR_HMAST_DFLT          0
#define PROCERR_HMAST_WMAC          1
#define PROCERR_HMAST_ENET          2
#define PROCERR_HMAST_PCIENDPT      3
#define PROCERR_HMAST_LOCAL         4
#define PROCERR_HMAST_CPU           5
#define PROCERR_HMAST_PCITGT        6
                                    
#define PROCERR_HMAST_S             0
#define PROCERR_HWRITE              0x00000010
#define PROCERR_HSIZE               0x00000060
#define PROCERR_HSIZE_S             5
#define PROCERR_HTRANS              0x00000180
#define PROCERR_HTRANS_S            7
#define PROCERR_HBURST              0x00000e00
#define PROCERR_HBURST_S            9



/*
 * Clock Control
 */
#define AR531XPLUS_PLLC_CTL         (AR531XPLUS_DSLBASE + 0x0064)
#define AR531XPLUS_PLLV_CTL         (AR531XPLUS_DSLBASE + 0x0068)
#define AR531XPLUS_CPUCLK           (AR531XPLUS_DSLBASE + 0x006c)
#define AR531XPLUS_AMBACLK          (AR531XPLUS_DSLBASE + 0x0070)
#define AR531XPLUS_SYNCCLK          (AR531XPLUS_DSLBASE + 0x0074)
#define AR531XPLUS_DSL_SLEEP_CTL    (AR531XPLUS_DSLBASE + 0x0080)
#define AR531XPLUS_DSL_SLEEP_DUR    (AR531XPLUS_DSLBASE + 0x0084)

/* PLLc Control fields */
#define PLLC_REF_DIV_M              0x00000003
#define PLLC_REF_DIV_S              0
#define PLLC_FDBACK_DIV_M           0x0000007C
#define PLLC_FDBACK_DIV_S           2
#define PLLC_ADD_FDBACK_DIV_M       0x00000080
#define PLLC_ADD_FDBACK_DIV_S       7
#define PLLC_CLKC_DIV_M             0x0001c000
#define PLLC_CLKC_DIV_S             14
#define PLLC_CLKM_DIV_M             0x00700000
#define PLLC_CLKM_DIV_S             20

/* CPU CLK Control fields */
#define CPUCLK_CLK_SEL_M            0x00000003
#define CPUCLK_CLK_SEL_S            0
#define CPUCLK_CLK_DIV_M            0x0000000c
#define CPUCLK_CLK_DIV_S            2

/* AMBA CLK Control fields */
#define AMBACLK_CLK_SEL_M           0x00000003
#define AMBACLK_CLK_SEL_S           0
#define AMBACLK_CLK_DIV_M           0x0000000c
#define AMBACLK_CLK_DIV_S           2

#if defined(COBRA_EMUL)
#define AR531XPLUS_AMBA_CLOCK_RATE  20000000
#define AR531XPLUS_CPU_CLOCK_RATE   40000000
#else
#if defined(DEFAULT_PLL)
#define AR531XPLUS_AMBA_CLOCK_RATE  40000000
#define AR531XPLUS_CPU_CLOCK_RATE   40000000
#else
#define AR531XPLUS_AMBA_CLOCK_RATE  92000000
#define AR531XPLUS_CPU_CLOCK_RATE   184000000
#endif /* ! DEFAULT_PLL */
#endif /* ! COBRA_EMUL */

#define AR531XPLUS_UART_CLOCK_RATE  AR531XPLUS_AMBA_CLOCK_RATE
#define AR531XPLUS_SDRAM_CLOCK_RATE AR531XPLUS_AMBA_CLOCK_RATE

/*
 * The UART computes baud rate as:
 *   baud = clock / (16 * divisor)
 * where divisor is specified as a High Byte (DLM) and a Low Byte (DLL).
 */
#define DESIRED_BAUD_RATE           38400

/*
 * The WATCHDOG value is computed as
 *  10 seconds * AR531X_WATCHDOG_CLOCK_RATE
 */
#define DESIRED_WATCHDOG_SECONDS    10
#define AR531X_WATCHDOG_TIME \
        (DESIRED_WATCHDOG_SECONDS * AR531X_WATCHDOG_CLOCK_RATE)


#define CLOCKCTL_UART0  0x0010  /* enable UART0 external clock */


 /*
 * Applicable "PCICFG" bits for WLAN(s).  Assoc status and LED mode.
 */
#define AR531X_PCICFG               (AR531X_RESETTMR + 0x00b0)
#define ASSOC_STATUS_M              0x00000003
#define ASSOC_STATUS_NONE           0
#define ASSOC_STATUS_PENDING        1   
#define ASSOC_STATUS_ASSOCIATED     2
#define LED_MODE_M                  0x0000001c
#define LED_BLINK_THRESHOLD_M       0x000000e0
#define LED_SLOW_BLINK_MODE         0x00000100

/*
 * GPIO
 */

#define AR531XPLUS_GPIO_DI          (AR531XPLUS_DSLBASE + 0x0088)
#define AR531XPLUS_GPIO_DO          (AR531XPLUS_DSLBASE + 0x0090)
#define AR531XPLUS_GPIO_CR          (AR531XPLUS_DSLBASE + 0x0098)
#define AR531XPLUS_GPIO_INT         (AR531XPLUS_DSLBASE + 0x00a0)

#define GPIO_CR_M(x)                (1 << (x))                  /* mask for i/o */
#define GPIO_CR_O(x)                (1 << (x))                  /* output */
#define GPIO_CR_I(x)                (0 << (x))                  /* input */

#define GPIO_INT(x,Y)               ((x) << (8 * (Y)))          /* interrupt enable */
#define GPIO_INT_M(Y)               ((0x3F) << (8 * (Y)))       /* mask for int */
#define GPIO_INT_LVL(x,Y)           ((x) << (8 * (Y) + 6))      /* interrupt level */
#define GPIO_INT_LVL_M(Y)           ((0x3) << (8 * (Y) + 6))    /* mask for int level */

#define AR531XPLUS_RESET_GPIO       5
#define AR531XPLUS_NUM_GPIO         22

    
/* 
 *  PCI Clock Control
 */     
 
#define AR531XPLUS_PCICLK           (AR531XPLUS_DSLBASE + 0x00a4)

#define PCICLK_INPUT_M              0x3
#define PCICLK_INPUT_S              0
                         
#define PCICLK_PLLC_CLKM            0
#define PCICLK_PLLC_CLKM1           1
#define PCICLK_PLLC_CLKC            2
#define PCICLK_REF_CLK              3 

#define PCICLK_DIV_M                0xc
#define PCICLK_DIV_S                2
                         
#define PCICLK_IN_FREQ              0
#define PCICLK_IN_FREQ_DIV_6        1
#define PCICLK_IN_FREQ_DIV_8        2
#define PCICLK_IN_FREQ_DIV_10       3 

/*
 * Observation Control Register
 */
#define AR531XPLUS_OCR              (AR531XPLUS_DSLBASE + 0x00b0)
#define OCR_GPIO0_IRIN              0x0040
#define OCR_GPIO1_IROUT             0x0080
#define OCR_GPIO3_RXCLR             0x0200

/* 
 *  General Clock Control
 */     
 
#define AR531XPLUS_MISCCLK          (AR531XPLUS_DSLBASE + 0x00b4)
#define MISCCLK_PLLBYPASS_EN        0x00000001
#define MISCCLK_PROCREFCLK          0x00000002

/*
 * SDRAM Controller
 *   - No read or write buffers are included.
 */
#define AR531XPLUS_MEM_CFG          (AR531XPLUS_SDRAMCTL + 0x00)
#define AR531XPLUS_MEM_CTRL         (AR531XPLUS_SDRAMCTL + 0x0c)
#define AR531XPLUS_MEM_REF          (AR531XPLUS_SDRAMCTL + 0x10)

#define SDRAM_DATA_WIDTH_M          0x00006000
#define SDRAM_DATA_WIDTH_S          13

#define SDRAM_COL_WIDTH_M           0x00001E00
#define SDRAM_COL_WIDTH_S           9

#define SDRAM_ROW_WIDTH_M           0x000001E0
#define SDRAM_ROW_WIDTH_S           5

#define SDRAM_BANKADDR_BITS_M       0x00000018
#define SDRAM_BANKADDR_BITS_S       3


/*
 * SDRAM Memory Refresh (MEM_REF) value is computed as:
 * MEMCTL_SREFR = (Tr * hclk_freq) / R
 * where Tr is max. time of refresh of any single row
 * R is number of rows in the DRAM
 * For most 133MHz SDRAM parts, Tr=64ms, R=4096 or 8192
 */
#if defined(COBRA_EMUL)
#define AR531XPLUS_SDRAM_MEMORY_REFRESH_VALUE  0x96
#else 
#if defined(DEFAULT_PLL)
#define AR531XPLUS_SDRAM_MEMORY_REFRESH_VALUE  0x200
#else
#define AR531XPLUS_SDRAM_MEMORY_REFRESH_VALUE  0x61a
#endif /* ! DEFAULT_PLL */
#endif 

#if defined(AR531XPLUS)

#define AR531XPLUS_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
#define AR531XPLUS_SDRAM_DATA_WIDTH     16  /* bits */   
#define AR531XPLUS_SDRAM_COL_WIDTH      8
#define AR531XPLUS_SDRAM_ROW_WIDTH      12

#else

#define AR531XPLUS_SDRAM_DDR_SDRAM      0   /* Not DDR SDRAM */
#define AR531XPLUS_SDRAM_DATA_WIDTH     16
#define AR531XPLUS_SDRAM_COL_WIDTH      8
#define AR531XPLUS_SDRAM_ROW_WIDTH      12

#endif /* ! AR531XPLUS */

/*
 * SPI Flash Interface Registers
 */

#define AR531XPLUS_SPI_CTL      (AR531XPLUS_SPI + 0x00)
#define AR531XPLUS_SPI_OPCODE   (AR531XPLUS_SPI + 0x04)
#define AR531XPLUS_SPI_DATA     (AR531XPLUS_SPI + 0x08)

#define SPI_CTL_START           0x00000100
#define SPI_CTL_BUSY            0x00010000
#define SPI_CTL_TXCNT_MASK      0x0000000f
#define SPI_CTL_RXCNT_MASK      0x000000f0
#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
#define SPI_CTL_SIZE_MASK       0x00060000

#define SPI_CTL_CLK_SEL_MASK    0x03000000
#define SPI_OPCODE_MASK         0x000000ff

/* 
 * PCI-MAC Configuration registers 
 */
#define PCI_MAC_RC              (AR531XPLUS_PCI + 0x4000) 
#define PCI_MAC_SCR             (AR531XPLUS_PCI + 0x4004)
#define PCI_MAC_INTPEND         (AR531XPLUS_PCI + 0x4008)
#define PCI_MAC_SFR             (AR531XPLUS_PCI + 0x400C)
#define PCI_MAC_PCICFG          (AR531XPLUS_PCI + 0x4010)
#define PCI_MAC_SREV            (AR531XPLUS_PCI + 0x4020)

#define PCI_MAC_RC_MAC          0x00000001
#define PCI_MAC_RC_BB           0x00000002

#define PCI_MAC_SCR_SLMODE_M    0x00030000
#define PCI_MAC_SCR_SLMODE_S    16        
#define PCI_MAC_SCR_SLM_FWAKE   0         
#define PCI_MAC_SCR_SLM_FSLEEP  1         
#define PCI_MAC_SCR_SLM_NORMAL  2         

#define PCI_MAC_SFR_SLEEP       0x00000001

#define PCI_MAC_PCICFG_SPWR_DN  0x00010000

 


/*
 * PCI Bus Interface Registers
 */
#define AR531XPLUS_PCI_1MS_REG      (AR531XPLUS_PCI + 0x0008)
#define AR531XPLUS_PCI_1MS_MASK     0x3FFFF         /* # of AHB clk cycles in 1ms */

#define AR531XPLUS_PCI_MISC_CONFIG  (AR531XPLUS_PCI + 0x000c)
#define AR531XPLUS_PCIMISC_TXD_EN   0x00000001      /* Enable TXD for fragments */
#define AR531XPLUS_PCIMISC_CFG_SEL  0x00000002      /* mem or config cycles */
#define AR531XPLUS_PCIMISC_GIG_MASK 0x0000000C      /* bits 31-30 for pci req */
#define AR531XPLUS_PCIMISC_RST_MODE 0x00000030
#define AR531XPLUS_PCIRST_INPUT     0x00000000      /* 4:5=0 rst is input */
#define AR531XPLUS_PCIRST_LOW       0x00000010      /* 4:5=1 rst to GND */
#define AR531XPLUS_PCIRST_HIGH      0x00000020      /* 4:5=2 rst to VDD */
#define AR531XPLUS_PCIGRANT_EN      0x00000000      /* 6:7=0 early grant en */
#define AR531XPLUS_PCIGRANT_FRAME   0x00000040      /* 6:7=1 grant waits 4 frame */
#define AR531XPLUS_PCIGRANT_IDLE    0x00000080      /* 6:7=2 grant waits 4 idle */
#define AR531XPLUS_PCIGRANT_GAP     0x00000000      /* 6:7=2 grant waits 4 idle */