ar531x.h

atheros ar531x watchdog driver

#else

/*
 * Add support for Cobra
 *
 * AR531XPLUSreg.h Register definitions for Atheros AR5311 and AR5312 chipsets.
 *   - WLAN registers are listed in
 *         hal/ar5211/ar5211Reg.h
 *         hal/ar5212/ar5212Reg.h
 *   - Ethernet registers are listed in ar531xenet.h
 *   - Standard UART is 16550 compatible.
 */


/*
 * Address map
 */
#define AR531XPLUS_SDRAM0           0x00000000      /* DRAM */
#define AR531XPLUS_SPI_READ         0x08000000      /* SPI FLASH */
#define AR531XPLUS_WLAN0            0xB0000000      /* Wireless MMR */
#define AR531XPLUS_PCI              0xB0100000      /* PCI MMR */
#define AR531XPLUS_SDRAMCTL         0xB0300000      /* SDRAM MMR */
#define AR531XPLUS_LOCAL            0xB0400000      /* LOCAL BUS MMR */
#define AR531XPLUS_ENET0            0xB0500000      /* ETHERNET MMR */
#define AR531XPLUS_DSLBASE          0xB1000000      /* RESET CONTROL MMR */
#define AR531XPLUS_UART0            0xB1100003      /* UART MMR */
#define AR531XPLUS_SPI              0xB1300000      /* SPI FLASH MMR */
#define AR531XPLUS_FLASHBT          0xBfc00000      /* ro boot alias to FLASH */
#define AR531XPLUS_RAM1             0x40000000      /* ram alias */
#define AR531XPLUS_PCIEXT           0x80000000      /* pci external */
#define AR531XPLUS_RAM2             0xc0000000      /* ram alias */
#define AR531XPLUS_RAM3             0xe0000000      /* ram alias */

#define AR531X_ENET0  AR531XPLUS_ENET0       
#define AR531X_ENET1  0 
/*
 * Reset Register
 */
#define AR531XPLUS_COLD_RESET       (AR531XPLUS_DSLBASE + 0x0000)

/* Cold Reset */
#define RESET_COLD_AHB              0x00000001
#define RESET_COLD_APB              0x00000002
#define RESET_COLD_CPU              0x00000004
#define RESET_COLD_CPUWARM          0x00000008
#define RESET_SYSTEM                (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB)      /* full system */

/* Warm Reset */

#define AR531XPLUS_RESET            (AR531XPLUS_DSLBASE + 0x0004)
#define AR531X_RESET AR531XPLUS_RESET

#define RESET_WARM_WLAN0_MAC        0x00000001      /* warm reset WLAN0 MAC */
#define RESET_WARM_WLAN0_BB         0x00000002      /* warm reset WLAN0 BaseBand */
#define RESET_MPEGTS_RSVD           0x00000004      /* warm reset MPEG-TS */
#define RESET_PCIDMA                0x00000008      /* warm reset PCI ahb/dma */
#define RESET_MEMCTL                0x00000010      /* warm reset memory controller */
#define RESET_LOCAL                 0x00000020      /* warm reset local bus */
#define RESET_I2C_RSVD              0x00000040      /* warm reset I2C bus */
#define RESET_SPI                   0x00000080      /* warm reset SPI interface */
#define RESET_UART0                 0x00000100      /* warm reset UART0 */
#define RESET_IR_RSVD               0x00000200      /* warm reset IR interface */
#define RESET_EPHY0                 0x00000400      /* cold reset ENET0 phy */
#define RESET_ENET0                 0x00000800      /* cold reset ENET0 mac */

#define AR531X_RESET_ENET0 RESET_ENET0
#define AR531X_RESET_EPHY0 RESET_EPHY0
#define AR531X_RESET_ENET1 0
#define AR531X_RESET_EPHY1 0

/*
 * AHB master arbitration control
 */
#define AR531XPLUS_AHB_ARB_CTL      (AR531XPLUS_DSLBASE + 0x0008)

#define ARB_CPU                     0x00000001      /* CPU, default */
#define ARB_WLAN                    0x00000002      /* WLAN */
#define ARB_MPEGTS_RSVD             0x00000004      /* MPEG-TS */
#define ARB_LOCAL                   0x00000008      /* LOCAL */
#define ARB_PCI                     0x00000010      /* PCI */
#define ARB_ETHERNET                0x00000020      /* Ethernet */
#define ARB_RETRY                   0x00000100      /* retry policy, debug only */

/*
 * Config Register
 */
#define AR531XPLUS_ENDIAN_CTL       (AR531XPLUS_DSLBASE + 0x000c)

#define CONFIG_AHB                  0x00000001      /* EC - AHB bridge endianess */
#define CONFIG_WLAN                 0x00000002      /* WLAN byteswap */
#define CONFIG_MPEGTS_RSVD          0x00000004      /* MPEG-TS byteswap */
#define CONFIG_PCI                  0x00000008      /* PCI byteswap */
#define CONFIG_MEMCTL               0x00000010      /* Memory controller endianess */
#define CONFIG_LOCAL                0x00000020      /* Local bus byteswap */
#define CONFIG_ETHERNET             0x00000040      /* Ethernet byteswap */

#define CONFIG_MERGE                0x00000200      /* CPU write buffer merge */
#define CONFIG_CPU                  0x00000400      /* CPU big endian */
#define CONFIG_PCIAHB               0x00000800
#define CONFIG_PCIAHB_BRIDGE        0x00001000
#define CONFIG_SPI                  0x00008000      /* SPI byteswap */
#define CONFIG_CPU_DRAM             0x00010000
#define CONFIG_CPU_PCI              0x00020000
#define CONFIG_CPU_MMR              0x00040000
#define CONFIG_BIG                  0x00000400      


/*
 * NMI control
 */
#define AR531XPLUS_NMI_CTL          (AR531XPLUS_DSLBASE + 0x0010)

#define NMI_EN  1

/*
 * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
 */
#define AR531XPLUS_SREV             (AR531XPLUS_DSLBASE + 0x0014)

#define AR531X_REV  AR531XPLUS_SREV

#define REV_MAJ                     0x00f0
#define REV_MAJ_S                   4
#define REV_MIN                     0x000f
#define REV_MIN_S                   0
#define REV_CHIP                    (REV_MAJ|REV_MIN)

#define AR531X_REV_MAJ REV_MAJ
#define AR531X_REV_MAJ_S REV_MAJ_S
#define AR531X_REV_MIN REV_MIN 
#define AR531X_REV_MIN_S REV_MIN_S 
#define REV_CHIP                    (REV_MAJ|REV_MIN)
/*
 * Need these defines to determine true number of ethernet MACs
 */
#define AR5212_AR5312_REV2      0x0052          /* AR5312 WMAC (AP31) */
#define AR5212_AR5312_REV7      0x0057          /* AR5312 WMAC (AP30-040) */
#define AR5212_AR2313_REV8      0x0058          /* AR2313 WMAC (AP43-030) */
#define AR531X_RADIO_MASK_OFF  0xc8
#define AR531X_RADIO0_MASK     0x0003
#define AR531X_RADIO1_MASK     0x000c
#define AR531X_RADIO1_S        2 

/* Major revision numbers, bits 7..4 of Revision ID register */
#define AR531X_REV_MAJ_AR5312          0x4
#define AR531X_REV_MAJ_AR2313          0x5

/*
 * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
 * should be considered available.  The AR5312 supports 2 enet MACS,
 * even though many reference boards only actually use 1 of them
 * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
 * The AR2312 supports 1 enet MAC.
 */
#define AR531X_NUM_ENET_MAC             1

/*
 * Interface Enable
 */
#define AR531XPLUS_IF_CTL           (AR531XPLUS_DSLBASE + 0x0018)

#define IF_MASK                     0x00000007
#define IF_DISABLED                 0
#define IF_PCI                      1
#define IF_TS_LOCAL                 2
#define IF_ALL                      3   /* only for emulation with separate pins */
#define IF_LOCAL_HOST               0x00000008
#define IF_PCI_HOST                 0x00000010
#define IF_PCI_INTR                 0x00000020
#define IF_PCI_CLK_MASK             0x00030000
#define IF_PCI_CLK_INPUT            0 
#define IF_PCI_CLK_OUTPUT_LOW       1
#define IF_PCI_CLK_OUTPUT_CLK       2
#define IF_PCI_CLK_OUTPUT_HIGH      3
#define IF_PCI_CLK_SHIFT            16 
 
                
/* Major revision numbers, bits 7..4 of Revision ID register */
#define REV_MAJ_AR5311              0x01
#define REV_MAJ_AR5312              0x04
#define REV_MAJ_AR5315              0x0B

/*
 * APB Interrupt control
 */

#define AR531XPLUS_ISR              (AR531XPLUS_DSLBASE + 0x0020)
#define AR531XPLUS_IMR              (AR531XPLUS_DSLBASE + 0x0024)
#define AR531XPLUS_GISR             (AR531XPLUS_DSLBASE + 0x0028)

#define ISR_UART0                   0x0001           /* high speed UART */
#define ISR_I2C_RSVD                0x0002           /* I2C bus */
#define ISR_SPI                     0x0004           /* SPI bus */
#define ISR_AHB                     0x0008           /* AHB error */
#define ISR_APB                     0x0010           /* APB error */
#define ISR_TIMER                   0x0020           /* timer */
#define ISR_GPIO                    0x0040           /* GPIO */
#define ISR_WD                      0x0080           /* watchdog */
#define ISR_IR_RSVD                 0x0100           /* IR */
                                
#define IMR_UART0                   ISR_UART0
#define IMR_I2C_RSVD                ISR_I2C_RSVD
#define IMR_SPI                     ISR_SPI
#define IMR_AHB                     ISR_AHB
#define IMR_APB                     ISR_APB
#define IMR_TIMER                   ISR_TIMER
#define IMR_GPIO                    ISR_GPIO
#define IMR_WD                      ISR_WD
#define IMR_IR_RSVD                 ISR_IR_RSVD

#define GISR_MISC                   0x0001
#define GISR_WLAN0                  0x0002
#define GISR_MPEGTS_RSVD            0x0004
#define GISR_LOCALPCI               0x0008
#define GISR_WMACPOLL               0x0010
#define GISR_TIMER                  0x0020
#define GISR_ETHERNET               0x0040

/*
 * Interrupt routing from IO to the processor IP bits
 * Define our inter mask and level
 */
#define AR531XPLUS_INTR_MISCIO      SR_IBIT3
#define AR531XPLUS_INTR_WLAN0       SR_IBIT4
#define AR531XPLUS_INTR_ENET0       SR_IBIT5
#define AR531XPLUS_INTR_LOCALPCI    SR_IBIT6
#define AR531XPLUS_INTR_WMACPOLL    SR_IBIT7
#define AR531XPLUS_INTR_COMPARE     SR_IBIT8

/*
 * Timers
 */
#define AR531XPLUS_TIMER            (AR531XPLUS_DSLBASE + 0x0030)
#define AR531XPLUS_RELOAD           (AR531XPLUS_DSLBASE + 0x0034)
#define AR531XPLUS_WD               (AR531XPLUS_DSLBASE + 0x0038)
#define AR531XPLUS_WDC              (AR531XPLUS_DSLBASE + 0x003c)

#define WDC_AHB_INTR                0x00000004               /* AHB error interrupt on watchdog */
#define WDC_RESET                   0x00000002               /* reset on watchdog */
#define WDC_NMI                     0x00000001               /* NMI on watchdog */
#define WDC_IGNORE_EXPIRATION       0x00000000

/*
 * Interface Debug
 */
#define AR531X_FLASHDBG             (AR531X_RESETTMR + 0x0040)
#define AR531X_MIIDBG               (AR531X_RESETTMR + 0x0044)


/*
 * CPU Performance Counters
 */
#define AR531XPLUS_PERFCNT0         (AR531XPLUS_DSLBASE + 0x0048)
#define AR531XPLUS_PERFCNT1         (AR531XPLUS_DSLBASE + 0x004c)

#define PERF_DATAHIT                0x0001  /* Count Data Cache Hits */
#define PERF_DATAMISS               0x0002  /* Count Data Cache Misses */
#define PERF_INSTHIT                0x0004  /* Count Instruction Cache Hits */
#define PERF_INSTMISS               0x0008  /* Count Instruction Cache Misses */
#define PERF_ACTIVE                 0x0010  /* Count Active Processor Cycles */
#define PERF_WBHIT                  0x0020  /* Count CPU Write Buffer Hits */
#define PERF_WBMISS                 0x0040  /* Count CPU Write Buffer Misses */
                                
#define PERF_EB_ARDY                0x0001  /* Count EB_ARdy signal */
#define PERF_EB_AVALID              0x0002  /* Count EB_AValid signal */
#define PERF_EB_WDRDY               0x0004  /* Count EB_WDRdy signal */
#define PERF_EB_RDVAL               0x0008  /* Count EB_RdVal signal */
#define PERF_VRADDR                 0x0010  /* Count valid read address cycles */
#define PERF_VWADDR                 0x0020  /* Count valid write address cycles */
#define PERF_VWDATA                 0x0040  /* Count valid write data cycles */

/*
 * AHB Error Reporting.
 */
#define AR531XPLUS_AHB_ERR0         (AR531XPLUS_DSLBASE + 0x0050)  /* error  */
#define AR531XPLUS_AHB_ERR1         (AR531XPLUS_DSLBASE + 0x0054)  /* haddr  */
#define AR531XPLUS_AHB_ERR2         (AR531XPLUS_DSLBASE + 0x0058)  /* hwdata */
#define AR531XPLUS_AHB_ERR3         (AR531XPLUS_DSLBASE + 0x005c)  /* hrdata */
#define AR531XPLUS_AHB_ERR4         (AR531XPLUS_DSLBASE + 0x0060)  /* status */

#define AHB_ERROR_DET               1   /* AHB Error has been detected,          */