opb_psram_v2_1_0.mpd

opb接口sdram控制器源码

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##
## Name     : opb_psram
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN opb_psram

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x80 
PARAMETER C_HIGHADDR = 0x000000ff, DT = std_logic_vector(0 to 31), BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_USER_ID_CODE = 3, DT = INTEGER
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_FAMILY = spartan-3, DT = STRING
PARAMETER C_PSRAM_DQ_WIDTH = 16, DT = INTEGER, ASSIGNMENT = OPTIONAL
PARAMETER C_PSRAM_A_WIDTH = 23, DT = INTEGER, ASSIGNMENT = OPTIONAL
PARAMETER C_PSRAM_LATENCY = 3, DT = INTEGER, ASSIGNMENT = OPTIONAL
PARAMETER C_DRIVE_STRENGTH = 1, DT = INTEGER, ASSIGNMENT = OPTIONAL

## Ports
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
PORT OPB_Clk = "", DIR = I, BUS = SOPB, SIGIS = CLK
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = I, BUS = SOPB, SIGIS = RST
PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT Sln_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT Sln_retry = Sl_retry, DIR = O, BUS = SOPB
PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
PORT PSRAM_Mem_CLK = "", DIR = IO, THREE_STATE = TRUE, TRI_I = PSRAM_Mem_CLK_I, TRI_O = PSRAM_Mem_CLK_O, TRI_T = PSRAM_Mem_CLK_T
PORT PSRAM_Mem_CLK_I = "", DIR = I
PORT PSRAM_Mem_CLK_O = "", DIR = O
PORT PSRAM_Mem_CLK_T = "", DIR = O
PORT PSRAM_Mem_DQ = "", DIR = IO, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE, THREE_STATE = TRUE, TRI_I = PSRAM_Mem_DQ_I, TRI_O = PSRAM_Mem_DQ_O, TRI_T = PSRAM_Mem_DQ_T, ENABLE = MULTI
PORT PSRAM_Mem_DQ_I = "", DIR = I, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_DQ_O = "", DIR = O, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_DQ_T = "", DIR = O, VEC = [(C_PSRAM_DQ_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_A = "", DIR = O, VEC = [(C_PSRAM_A_WIDTH-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_BE = "", DIR = O, VEC = [((C_PSRAM_DQ_WIDTH/8)-1):0], ENDIAN = LITTLE
PORT PSRAM_Mem_WE = "", DIR = O
PORT PSRAM_Mem_OEN = "", DIR = O
PORT PSRAM_Mem_CEN = "", DIR = O
PORT PSRAM_Mem_ADV = "", DIR = O
PORT PSRAM_Mem_WAIT = "", DIR = I
PORT PSRAM_Mem_CRE = "", DIR = O

END