states.vhd

来自「自己做的接金币小游戏」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.std_logic_signed.ALL;

entity states is
 port(
      los:in std_logic;
      start:in std_logic;
      suspond:in std_logic;
      stop:in std_logic;
      left:in std_logic;
      right:in std_logic;
      state:out std_logic_vector(4 downto 0)
      );
end entity states;

architecture behavioral of states is
begin
     state(0)<='1' when (start='0' and suspond='1' and stop='1')
     else '0';
     state(1)<='1' when (start='1' and suspond='0' and stop='1')
     else '0';
     state(2)<='1' when (((start='1' and suspond='1' and stop='0') or los='1'))
     else '0';
     state(3)<='1' when (left='1' and right='0')
     else '0';
     state(4)<='1' when (left='0' and right='1')
     else '0';
end behavioral;